PRELIMINARY
XRT79L71
402
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
STEP 5 - Enable the "Receive LAPD Interrupt" (Optional).
This step is optional. However, if this step is executed, then the XRT79L71 will generate an interrupt to the
Microprocessor anytime the Receive LAPD Controller block has completed its reception of a new PMDL
Message. The purpose of this interrupt is to notify the Microprocessor that the Receive LAPD Message buffer
contains a newly received LAPD/PMDL Message that needs to be read.
The procedure for enabling the "Receive LAPD Interrupt" is actually a "three-step" process.
STEP 5a - Enable the "DS3/E3 Framer" block interrupts - At the Operational Block Level.
This step is accomplished by setting Bit 2 (DS3/E3 Framer Block Interrupt Enable) to "1" as illustrated below.
This step enables the "DS3/E3 Framer" block for interrupt generation; at the "Operational Block" Level.
STEP 5b - Enable the "Receive DS3/E3 Framer" block Interrupts - At the Block Level.
This step is accomplished by setting Bit 7 (Receive DS3/E3 Framer Block Interrupt Enable), within the "Framer
Block Interrupt Enable" Register, to "1", as illustrated below.
This step enables the "Receive DS3/E3 Framer" block for interrupt generation, at the "Block" Level.
Receive E3 LAPD Status Register (Address = 0x1119)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxABORT
RxLAPDType[1:0]
RxCR
Type
RxFC
SError
End of
Message
Flag
Present
R/O
0
1
Operation Block Interrupt Enable Register - Byte 1 (Address = 0x0116)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
DS3/E3
LIU/JA
Block
Interrupt
Enable
DS3/E3
Framer
Block
Interrupt
Enable
Unused
R/O
R/W
R/O
0
1
0
Framer Block Interrupt Enable Register (Address = 0x1104)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
DS3/E3
Framer
Block
Interrupt
Enable
Receive
PLCP
Processor
Block
Interrupt
Enable
Unused
Transmit
DS3/E3
Framer
Block
Interrupt
Enable
One
Second
Interrupt
Enable
R/W
R/O
R/W
1
0
X