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PRELIMINARY
XRT79L71
548
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
STEP 2 - Determine whether this particular interrupt occurred within the "Transmit" or "Receive DS3/
E3 Framer" block.
This can be accomplished by reading out the contents of the "Framer Block Interrupt Status" Register. Since
we are discussing the "SSM Out-of-Sequence" Interrupt, then Bit 7 (Receive DS3/E3 Framer Block Interrupt
Status) should be set to "1" as depicted below.
STEP 3 - Determine which "Receive DS3/E3 Framer block" interrupt has been requested.
This is accomplished by reading out the contents of both the "Receive E3 Interrupt Status Register # 1 and # 2"
as depicted below.
NOTES:
1.
Since we are discussing the "SSM Out-of-Sequence" Interrupt, Bit 5 (SSM OOS Interrupt Status), within the
"Receive E3 Interrupt Status Register # 1 - G.832" has been set to "1" as depicted above.
Framer Block Interrupt Status Register (Address = 0x1105)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
DS3/E3
Framer
Block
Interrupt
Status
Receive
PLCP
Processor
Block
nterrupt
Status
Unused
Transmit
DS3/E3
Framer
Block
Interrupt
Status
One
Second
Interrupt
R/O
RUR
1
0
Receive E3 Interrupt Status Register # 1 - G.832 (Address = 0x1114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
SSM MSGI
nterrupt
Status
SSM OOS
Interrupt
Status
COFA
Interrupt
Status
Change in
OOF State
Interrupt
Status
Change in
LOF State
Interrupt
Status
Change in
LOS State
Interrupt
Status
Change in
AIS State
Interrupt
Status
R/O
RUR
0
1
0
Receive E3 Interrupt Status Register # 2 - G.832 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
Receive
Trail-Trace
Message
Interrupt
Status
Reserved
Detection of
FEBE/REI
Event
Interrupt
Status
Change in
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-8 Error
Interrupt
Status
Detection of
Framing
Byte Error
Interrupt
Status
RxPLD
Mismatch
Interrup
Status
R/O
RUR
R/O
RUR
0