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XRT79L71
PRELIMINARY
447
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Configuring the XRT79L71 to operate in Mode 4 (Nibble-Parallel/Loop-Timing) Mode
The user can configure the XRT79L71 to operate in Mode 4 by executing the following steps.
STEP 1 - Design your board such that the System-Side Terminal Equipment circuitry interfaces to the
Transmit Payload Data Input Interface in the manner as depicted above in Figure 212. STEP 2 - Configure the XRT79L71 to operate in the Nibble-Parallel Mode
This can be accomplished by setting the "NibIntf" input pin to a logic "HIGH".
STEP 3 - Configure the XRT79L71 to operate in the Loop-Timing Mode
This can be accomplished by setting Bits 1 and 0 (TimRefSel[1:0]) within the "Framer Operating Mode"
Register to "[0, 0]" as depicted below.
6.2.1.5
Mode 5 - Nibble-Parallel/Local-Timing/Frame Slave Mode Operation for the Transmit
Payload Data Input Interface Block
If the XRT79L71 is configured to operate in "Mode 5" then all of the following is true.
FIGURE 213. AN ILLUSTRATION OF THE BEHAVIOR OF THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR
MODE 4 (NIBBLE-PARALLEL/LOOP-TIMING) MODE OPERATION
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local
Loop Back
IsDS3
Internal
LOS
Enable
RESET
Direct
Mapped
ATM
Frame
Format
TimRefSel[1:0]
R/W
0
1
0
1
0
System-Side Terminal Equipment Signals
RxOutClk
Tx_End_of_Frame
E3_Nib_Clock_In
E3_Data_Out[3:0]
Payload Nibble [1059]
FA1 Byte, Nibble [0]
XRT79L71 Transmit Payload Data Input Interface Signals
E3 Frame Number N
E3 Frame Number N + 1
Note: TxNibFrame pulses high to denote
E3 Frame Boundary.
RxOutClk
TxNibFrame
TxNibClk
TxNib[3:0]
Payload Nibble [1059]
FA1 Byte, Nibble [0]
Sampling Edge of XRT79L71 Device
E3_OH_Ind
TxOH_Ind
TxOH_Ind toggles to
Denote Overhead Nibble