XRT79L71
PRELIMINARY
333
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Figure 153 indicates that the Transmit DS3/E3 LIU Block consists of the following functional blocks.
The HDB3 Encoder Block
The Jitter Attenuator (which can be configured to operate in either the Transmit or Receive Directions)
The Transmit Control Block
The Transmit Pulse Shaping Block
The Transmit Line Driver Block
The Transmit Drive Monitor Block
5.2.5.1
The HDB3 Encoder Block
The purpose of the HDB3 Encoder block is to encode the "outbound" E3 traffic into the "HDB3 Line Code". In
the case of the XRT79L71, the HDB3 Encoder block will always be enabled, and the user has no ability to
disable the HDB3 Encoder block.
5.2.5.2
The Jitter Attenuator Block
The XRT79L71 includes a Jitter Attenuator block that can be configured to operate in either the Transmit
Direction (e.g., within the Transmit DS3/E3 LIU Block) or in the Receive Direction (e.g., within the Receive
DS3/E3 LIU Block). The purpose of the Jitter Attenuator block is to permit the XRT79L71 to comply with all of
the following "Jitter Transfer Characteristic" requirements.
Bellcore GR-499-CORE "Category II to Category II Interfaces" (DS3 Applications)
TBR-24 34Mbps D34U and D34S System Requirements (for E3 Applications)
FIGURE 153. ILLUSTRATION OF THE TRANSMIT DS3/E3 LIU BLOCK WITHIN THE XRT79L71
HDB3
Encoder
Block
HDB3
Encoder
Block
Jitter
Attenuator
Block
Jitter
Attenuator
Block
Timing
Control
Block
Timing
Control
Block
Transmit
Pulse
Shaping
Block
Transmit
Pulse
Shaping
Block
Transmit
Drive
Monitor
Block
Transmit
Drive
Monitor
Block
Line
Driver
Transmit
Control
Block
Transmit
Control
Block
MUX
From Transmit DS3/E3
Framer Block
TxLEV
TxON
LIU Remote Loop-back
Path
TTIP
TRING
DMO
MTIP
MRING
Internal Tx
Monitoring
NOTE: Jitter Attenuator Block
Can be configured to operate in Transmit
Or Receive Path
TAOS