
XRT79L71
PRELIMINARY
371
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The CERJAC Tester was configured to internally generate a E3 signal, which was filled with an un-framed
2^23-1 PRBS pattern.
The E3 line signal was then routed to the ME-1005 75W Coaxial Cable Simulator (from Mountain Engineering).
The Cable Simulator could either be configured to 0 to 12dB of "shaped" loss into the E3 line signal.
Next, this attenuated signal will be routed to one of the inputs of a summing network. The output of the
function-generator (the output frequency of which is set at half the bit-rate) will be applied to the other input.
This signal represents the "Interfering Tone" or "Noise" in this test. The summing network will add the "Noise"
signal to the "distorted signal", and will output this composite signal to the "Receive Input" of the XRT79L71
Evaluation Board.
NOTE: For E3 testing, the function generator was configured to generate a sinewave that has a frequency of 17.184MHz.
Test Results
Table 46 presents the "Interference Margin" Test results for E3 Applications.
5.3.1.9.3
Jitter Tolerance Capability of the Receive E3 LIU Block
5.3.1.10
Receive DS3/E3 LIU Block Interrupts
5.3.2
THE RECEIVE E3 FRAMER BLOCK
The Receive DS3/E3 Framer block is the second functional block (within the Receive Direction) of the
XRT79L71 that we will discuss for Clear-Channel Framer Applications.
6 presents an illustration of the
"Receive Direction" circuitry whenever the XRT79L71 has been configured to operate in the E3, ITU-T G.751
Clear-Channel Framer Mode, with the Receive DS3/E3 Framer block highlighted.
TABLE 46: INTERFERENCE MARGIN TEST RESULTS FOR E3 APPLICATIONS
TEST NUMBER
CABLE LENGTH (IN RECEIVE DIRECTION)
INTERFERENCE MARGIN TEST RESULTS
1
0dB
17dB
2
12.1dB
14dB