XRT79L71
PRELIMINARY
581
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Configuring the XRT79L71 to operate in the Nibble-Parallel Mode
The XRT79L71 can be configured to operate in the Nibble-Parallel Mode by executing the following steps.
STEP 1 - Design your board such that the System-Side Terminal Equipment circuitry interfaces to the
Receive Payload Data Input Interface in the manner as depicted above in Figure 268.
STEP 2 - Configure the XRT 79L71 to operate in the Nibble-Parallel Mode
This can be accomplished by setting the "NibIntf" input pin to a logic "HIGH".
NOTE: This step also configures the "Transmit Payload Data Input Interface" block to operate in the "Nibble-Parallel Mode".
7.0
DIAGNOSTIC OPERATION - CLEAR-CHANNEL FRAMER MODE
If the XRT79L71 has been configured to operate in the Clear-Channel Framer mode, then there are numerous
"diagnostic" resources that are available to the user. These resources include (1) a variety of loop-back modes
available, and (2) a PRBS Generator and Receiver.
7.1
THE LOOPBACK MODES AVAILABLE WITHIN THE XRT79L71
In all, If the XRT79L71 has been configured to operate in the Clear-Channel Framer Mode, then it will support
the following loop-back modes.
The LIU Analog Local Loop-back Mode
The LIU Digital Local Loop-back Mode
The LIU Remote Loop-back Mode
The Framer Local Loop-back Mode
FIGURE 266. AN ILLUSTRATION OF THE BEHAVIOR OF THE "SYSTEM-SIDE TERMINAL EQUIPMENT" SIGNALS FOR
"NIBBLE-PARALLEL MODE" OPERATION
System-Side Terminal Equipment Signals
XRT79L71 Transmit Payload Data Input Interface Signals
E3 Frame Number N
E3 Frame Number N + 1
Note: RxFrame pulses high to denote
E3 Frame Boundary.
Rx_Start_of_Frame
E3_Nib_Clock_In
E3_Data_In[3:0]
FA1 Byte – Bits 1 - 4
FA1 Byte – Bits 5 - 8
RxClk
RxFrame
RxNib[3:0]
FA1 Byte – Bits 1 - 4
FA1 Byte – Bits 5 - 8
RxOH_Ind
Rx_E3_Overhead_Ind