
PRELIMINARY
XRT79L71
414
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
RxCLK/
RxNibClk
A6
O
Receive Payload Data Output Interface -Clock Output Pin:
The exact behavior of this signal depends upon whether the XRT79L71
has been configured to operate in the "Serial Mode" or in the "Nibble-
Parallel Mode", as described below.
Serial Mode Operation - RxCLK
If the Receive Payload Data Output Interface block has been configured
to operate in the Serial Mode, then this signal will be a 34.368MHz clock
output signal. The Receive Payload Data Output Interface block will
update the data (via the RxSer output pin) upon the rising edge of this
clock signal.
For "Serial Mode" operation, the user is advised to design (or configure)
the System-Side Terminal Equipment to sample the data on the "RxSer"
output pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation - RxNibClk
If the Receive Payload Data Output Interface block has been configured
to operate in the Nibble-Parallel Mode, then the XRT79L71 will pulse this
output pin 384 times for each inbound E3 frame. The Receive Payload
Data Output Interface block will update the data (via the "RxNib[3:0]"
output pins upon the falling edge of this clock signal.
For "Nibble-Parallel Mode" operation, the user is advised to design (or
configure) the System-Side Terminal Equipment to sample the data on
the "RxNib[3:0]" output pins, upon the rising edge of this clock signal.
NOTE: This output clock signal is ultimately derived from the Recovered
Clock signal (via the Receive DS3/E3 LIU Block).
TABLE 51: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE
BLOCK
SIGNAL NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION