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PRELIMINARY
XRT79L71
98
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Once the user executes these five steps, then the Transmit DS3 Framer block will simply (1) accept the C-bit
values from the DS3 data-stream that it receives from the Transmit Payload Interface block, and (2) will insert
these same values into the C-bit positions within its outbound DS3 data-stream.
4.2.2
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK
The Transmit Overhead Data Input Interface block is the second functional block within the Transmit Direction
of the XRT79L71 that we will discuss for DS3 Clear-Channel Framer Applications. Figure 43 presents an
illustration of the Transmit Direction circuitry whenever the XRT79L71 has been configured to operate in the
DS3 Clear-Channel Framer Mode, with the Transmit Overhead Data Input Interface block highlighted.
Some Background Information
Transmit DS3 F-Bit Mask # 4 Register (Indirect Address = 0xnE, 0x39; Direct Address = 0x1139)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UDL Bit # 3
(C23)
UDL Bit # 2
(C22)
UDL Bit # 1
(C21)
X Bit # 2
FEAC Bit
(C13)
NA Bit (C12)
AIC Bit
(C11)
X Bit # 1
R/W
0
1
0
1
FIGURE 43. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK HIGHLIGHTED)
Transmit
Payload Data
Input
Interface
Block
Transmit
Payload Data
Input
Interface
Block
Transmit
DS3/E3
Framer
Block
Transmit
DS3/E3
Framer
Block
Tranmit
DS3/E3
LIU Block
Tranmit
DS3/E3
LIU Block
TxSer
TxNib[3:0]
TxInClk
TRING
TTIP
Transmit
Overhead Data
Input Interface
Block
Transmit
Overhead Data
Input Interface
Block
TxOHClk
TxOHIns
TxOHInd
TxOH
TxOHEnable
TxOHFrame
TxNibClk
TxFrame
Tx LAPD
Controller
Block
Tx LAPD
Controller
Block
From Microprocessor
Interface Block
Tx LAPD
Buffer
(90 Bytes)
Tx LAPD
Buffer
(90 Bytes)
Tx FEAC
Processor
Block
Tx FEAC
Processor
Block