
XRT79L71
PRELIMINARY
195
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
It will generate the Change of LOS Condition Interrupt.
NOTE: The XRT79L71 will indicate that it is generating this interrupt by (1) asserting the Interrupt Request output pin, and
(2) by setting Bit 1 (Change of LOS Condition Interrupt), within the LIU Interrupt Status Register to "1" as depicted
below.
The LOS Defect Clearance Criteria
Once the Analog LOS Detector is currently declaring the LOS Defect condition, it will only clear the LOS Defect
condition, whenever it determines that the amplitude of the incoming DS3 line signal is greater than _ (when
measured across the RTIP and RRING input pins).
The Receive DS3/E3 LIU Block will indicate (to the outside world) that the Analog LOS Detector is clearing the
LOS defect condition, by doing all of the following.
It will set Bit 5 (Digital LOS Defect Declared), within the LIU Alarm Status Register to "1" as depicted below.
LIU Alarm Status Register (Address = 0x1303)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Digital LOS
Defect
Declared
Analog LOS
Defect
Declared
FL (FIFO
Limit) Alarm
Declared
Receive LOL
Defect
Declared
Receive LOS
Defect
Declared -
Receive
DS3/E3 LIU
Block
Transmit
DMO Condi-
tion
R/O
0
1
0
1
0
LIU Interrupt Status Register (Address = 0x1302)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of
FL
Condition
Interrupt
Status
Change of
LOL
Condition
Interrupt
Status
Change of
LOS
Condition
Interrupt
Status
Change of
DMO
Condition
Interrupt
Status
R/O
RUR
0
1
0
LIU Alarm Status Register (Address = 0x1303)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Digital LOS
Defect
Declared
Analog LOS
Defect
Declared
FL (FIFO
Limit) Alarm
Declared
Receive LOL
Defect
Declared
Receive LOS
Defect
Declared -
Receive
DS3/E3 LIU
Block
Transmit
DMO Condi-
tion
R/O
0
1
0
X
0