
PRELIMINARY
XRT79L71
572
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
The Receive Payload Data Output Interface block is the seventh (and final) functional block (within the Receive
Direction) of the XRT79L71 that we will discuss for Clear-Channel Framer Applications. Figure 261 presents
an illustration of the "Receie Direction" circuitry whenever the XRT79L71 has been configured to operate in the
E3, ITU-T G.832 Clear-Channel Framer Mode, with the "Receive Payload Data Output Interface" block
highlighted.
The purpose of the "Receive Payload Data Output Interface" block is to output payload data that has been
extracted from the incoming E3 data-stream that has been received and processed by the "Receive Direction"
circuitry within the XRT79L71.
In order to accomplish this, the Receive Payload Data Output Interface block has numerous output pins.
Table 73 presents a list and a brief definition of each of these pins.
FIGURE 261. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER
MODE (WITH THE "RECEIVE PAYLOAD DATA OUTPUT INTERFACE" BLOCK HIGHLIGHTED)
Receive
Payload Data
Input
Interface
Block
Receive
Payload Data
Input
Interface
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
RxSer
RxNib[3:0]
RxClk
RRING
RTIP
Receive
Overhead Data
Input Interface
Block
Receive
Overhead Data
Input Interface
Block
RxOHClk
RxOHInd
RxOH
RxOHEnable
RxOHFrame
RxNibClk
RxFrame
Rx LAPD
Controller
Block
Rx LAPD
Controller
Block
From Microprocessor
Interface Block
Rx LAPD
Buffer
(90 Bytes)
Rx LAPD
Buffer
(90 Bytes)
Rx TTM
Controller
Block
Rx TTM
Controller
Block
Rx SSM
Controller
Block
Rx SSM
Controller
Block