
PRELIMINARY
XRT79L71
90
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Configuring the XRT79L71 to operate in Mode 6 (Nibble-Parallel/Local-Timing/Frame Master Mode)
The user can configure the XRT79L71 to operate in Mode 6 by executing the following steps.
STEP 1 - Design your board such that the System-Side Terminal Equipment circuitry interfaces to the
Transmit Payload Data Input Interface in the manner as depicted above in Figure 40. STEP 2 - Configure the XRT79L71 to operate in the Nibble-Parallel Mode
This can be accomplished by setting the NibIntf input pin to a logic "High".
STEP 3 - Configure the XRT79L71 to operate in the Local-Timing/Frame Master Mode
This can be accomplished by setting Bits 1 and 0 (TimRefSel[1:0]) within the Framer Operating Mode Register
to [1, X] as depicted below.
4.2.1.7
Operating the Transmit Payload Data Input Interface in the Gapped Clock Mode
If the Transmit Payload Data Input Interface, within the XRT79L71, has been configured to operate in any one
FIGURE 41. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE
6 (NIBBLE-PARALLEL/LOCAL-TIMING/FRAME MASTER) MODE OPERATION
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local Loop
Back
IsDS3
Internal LOS
Enable
RESET
Direct
Mapped
ATM
Frame For-
mat
TimRefSel[1:0]
R/W
0
1
0
1
X
1
X
System Side Terminal Equipment Signals
XRT79L71 Transmit Payload Data Input Interface Signals
DS3 Frame Number N
DS3 Frame Number N + 1
Note: TxNibFrame pulses high to denote
DS3 Frame Boundary.
TxInClk
Tx_Start_of_Frame
DS3_Nib_Clock_In
DS3_Data_Out[3:0]
Nibble [1175]
Nibble [0]
TxInClk
TxNibFrame
TxNibClk
TxNib[3:0]
Nibble [1175]
Nibble [0]
Sampling Clock Edge