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XRT79L71
PRELIMINARY
75
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Figure 31 presents an illustration of the System-Side Terminal Equipment/Transmit Payload Data Input
Interface signals for Mode 1 Operation.
Configuring the XRT79L71 to operate in Mode 1 (Serial/Loop-Timing)
The user can configure the XRT79L71 to operate in Mode 1 by executing the following steps.
STEP 1 - Design your board such that the System-Side Terminal Equipment circuitry interfaces to the
Transmit Payload Data Input Interface in the manner as depicted above in Figure 31. STEP 2 - Configure the XRT79L71 to operate in the Serial Mode
This can be accomplished by setting the NibIntf input pin to a logic "Low".
NOTE: This step also configures the Receive Payload Data Output Interface block to operate in the Serial Mode.
STEP 3 - Configure the XRT79L71 to operate in the Loop-Timing Mode
This can be accomplished by setting Bits 1 and 0 (TimRefSel[1:0]) within the Framer Mode Operating Mode
Register to [0, 0] as depicted below.
FIGURE 31. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE
1 (SERIAL/LOOP-TIMING) MODE OPERATION
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local Loop
Back
IsDS3
Internal LOS
Enable
RESET
Direct
Mapped
ATM
Frame For-
mat
TimRefSel[1:0]
R/W
0
1
0
1
X
0
System-Side Terminal Equipment Signals
DS3_Clock_In
DS3_Data_Out
Tx_Start_of_Frame
DS3_Overhead_Ind
XRT79L71 Transmit Payload Data Input Interface Block Signals
RxOutClk
TxSer
TxFrame
TxOH_Ind
Payload[4702]
Payload[4703]
X-Bit
Payload[0]
Payload[4702]
Payload[4703]
X-Bit
Payload[0]
Note: X-Bit will not be processed by the
Transmit Payload Data Input Interface.
DS3 Frame Number N
DS3 Frame Number N + 1
Note: RxFrame pulses high to denote
DS3 Frame Boundary.
Note: TxOH_Ind pulses high to
denote Overhead Data
(e.g., the X-bit).