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XRT79L71
PRELIMINARY
389
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
It will generate the "Detection of BIP-4 Error" Interrupt request, by asserting the Interrupt Output pin (e.g., by
pulling it "LOW") and setting Bit 2 (Detection of BIP-4 Error Interrupt Status), within the Receive E3 Interrupt
Status Register # 2" to "1" as depicted below.
It will increment the "PMON P-bit/Parity Error Count" Register once of each E3 frame that is detemined to
have an erred BIP-4 nibble. The "PMON P-bit/Parity Error Count" Register is located at Address = 0x1154
and 0x1155. The bit-format for each of these registers is presented below.
NOTE: For instructions on how to read out these "Performance Monitor" Registers, please see Section 2.5. It will also increment the "One Second - P-bit/Parity Error Count - Accumulator" Register once for each
incoming E3 frame that is determined to have an erred BIP-4 Nibble. The "One Second - P-Bit/Parity Error
Count - Accumulator" Register is located at Address = 0x1170 and 0x1171. The bit-format for this 16-bit
register is presented below.
Receive E3 Interrupt Status Register # 2 - G.751 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-4
Error
Interrupt
Status
Detection of
FAS Bit
Error
Interrupt
Status
Reserved
R/O
RUR
R/O
0
1
0
PMON Parity/P-Bit Error Count Register - MSB (Address = 0x1154)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Parity_Error_Count_Upper_Byte[7:0]
RUR
0
PMON Parity/P-Bit Error Count Register - LSB (Address = 0x1155)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Parity_Error_Count_Lower_Byte[7:0]
RUR
0
One Second - Parity Error Accumulator Register - MSB (Address = 0x1170)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
One_Second_Parity_Error_Accum_MSB[7:0]
R/O
0