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PRELIMINARY
XRT79L71
530
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
The Receive E3 Framer block will also generate the Change in FERF/RDI Defect Condition Interrupt, by
asserting the Interrupt Output pin (e.g., by pulling it "Low") and setting Bit 3 (Change in FERF/RDI Defect
Condition Interrupt Status), within the Receive E3 Interrupt Status Register # 2 to "1" as depicted below.
6.3.2.6
DETECTING EM BYTE ERRORS
The Receive E3 Framer block has the responsibility for detecting and flagging the occurrence of EM byte
errors, as described below.
Processing at the Remote Terminal Equipment
As the remote terminal equipment is generating and transmitting the E3 data-stream that the local terminal
equipment will ultimately receive and process, it will compute the BIP-8 value over an entire E3 frame. The
results of this BIP-8 calculation will be inserted into the EM byte-position, within the very next outbound E3
frame. The purpose of the EM byte, is to support Performance Monitoring and Error Detection within the E3
data-stream, as it is transported from one terminal equipment to another.
Processing at the Local Terminal Equipment
As the Receive E3 Framer block receives a given E3 frame that was generated by the remote terminal
equipment will locally-compute its own BIP-8 value for this incoming E3 frame. Afterwards, the Receive E3
Framer block will compare its locally-computed BIP-8 value with the contents of the EM byte, within the very
next incoming E3 frame. If these two values match, then the Receive E3 Framer block will conclude that it has
received this particular E3 frame, in an un-erred manner. Conversely, if these two values DO NOT match, then
the Receive E3 Framer block will conclude that is has received this particular E3 frame, in an erred manner.
If the Receive E3 Framer block determines that the EM byte within a given E3 frame are erred, then it will do
the following.
It will generate the Detection of BIP-8 Error Interrupt request, by asserting the Interrupt Output pin (e.g., by
pulling it "Low") and setting Bit 2 (Detection of BIP-8 Error Interrupt Status), within the Receive E3 Interrupt
Status Register # 2 to "1" as depicted below.
Receive E3 Interrupt Status Register # 2 - G.832 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
RxTTB
Message
Interrupt
Status
Reserved
Detection of
FEBE Event
Interrupt
Status
Change in
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-8 Error
Interrupt
Status
Detection of
Framing
Byte Error
Interrupt
Status
RxPLD
Mismatch
Interrupt
Status
R/O
RUR
R/O
RUR
0
1
0
Receive E3 Interrupt Status Register # 2 - G.832 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
RxTTB
Message
Interrupt
Status
Reserved
Detection of
FEBE Event
Interrupt
Status
Change in
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-8 Error
Interrupt
Status
Detection of
Framing
Byte Error
Interrupt
Status
RxPLD
Mismatch
Interrupt
Status
R/O
RUR
R/O
RUR
0
1
0