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XRT79L71
PRELIMINARY
229
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
This step enables the Receive DS3/E3 Framer block for interrupt generation, at the Block Level.
STEP 4c - Enable the Receive LAPD Interrupt at the Source Level.
This step is accomplished by setting Bit 1 (Receive LAPD Interrupt Enable), within the Receive DS3 LAPD
Control Register, as depicted below.
STEP 5 - Wait for the occurrence of the Receive LAPD Interrupt
STEP 6 - Service the Receive LAPD Interrupt
STEP 7 - Check and verify that there are no FCS (Frame Check Sequence) Errors within the LAPD/
PMDL Message that is residing within the Receive LAPD Message Buffer.
This can be accomplished by reading out and testing the state of Bit 2 (RxFCS Error) within the Receive DS3
LAPD Status Register as depicted below.
If this bit-field is set to "0", then the Receive LAPD Controller block has received this particular LAPD Message
that is residing within the Receive LAPD Message Buffer in an un-erred manner (e.g., there are no FCS errors
within this particular LAPD message).
Conversely, if this bit-field is set to "1", then the Receive LAPD
Controller block has received this particular LAPD Message that is residing within the Receive LAPD Message
Buffer in an erred manner.
Block Interrupt Enable Register (Address = 0x1104)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
DS3/E3
Framer
Block Inter-
rupt Enable
Receive
PLCP
Processor
Block
Interrupt
Enable
Unused
Transmit
DS3/E3
Framer
Block Inter-
rupt Enable
One Second
Interrupt
Enable
R/W
R/O
R/W
1
0
X
Receive DS3 LAPD Control Register (Address = 0x1118)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxLAPD
Any
Unused
Receive
LAPD
Enable
Receive
LAPD
Interrupt
Enable
Receive
LAPD
Interrupt
Status
R/W
R/O
R/W
RUR
0
1
0
Receive DS3 LAPD Status Register (Address = 0x1119)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxABORT
RxLAPDType[1:0]
RxCR Type
RxFCS Error
End of
Message
Flag Present
R/O
0
X
0
X
0