参数资料
型号: MT42L64M32D1KL-25 IT:A
厂商: Micron Technology Inc
文件页数: 10/164页
文件大小: 0K
描述: IC DDR2 SDRAM 2GBIT 168FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: 移动 LPDDR2 SDRAM
存储容量: 2G(64M x 32)
速度: 400MHz
接口: 并联
电源电压: 1.14 V ~ 1.3 V
工作温度: -25°C ~ 85°C
封装/外壳: 168-WFBGA
供应商设备封装: 168-FBGA(12x12)
包装: 散装
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Table 51:
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
Table 75:
Table 76:
Table 77:
Table 78:
Table 79:
Table 80:
Table 81:
Table 82:
Table 83:
Table 84:
Table 85:
Table 86:
Table 87:
Table 88:
Table 89:
Table 90:
Table 91:
Table 92:
Table 93:
Table 94:
Table 95:
Table 96:
Current State Bank n to Command to Bank n Truth Table ................................................................ 107
Current State Bank n to Command to Bank m Truth Table ............................................................... 109
DM Truth Table .............................................................................................................................. 112
Absolute Maximum DC Ratings ...................................................................................................... 113
Input/Output Capacitance ............................................................................................................. 113
Switching for CA Input Signals ........................................................................................................ 114
Switching for I DD4R ......................................................................................................................... 115
Switching for I DD4W ........................................................................................................................ 115
I DD Specification Parameters and Operating Conditions .................................................................. 115
Recommended DC Operating Conditions ....................................................................................... 117
Input Leakage Current ................................................................................................................... 118
Operating Temperature Range ........................................................................................................ 118
Single-Ended AC and DC Input Levels for CA and CS# Inputs ........................................................... 119
Single-Ended AC and DC Input Levels for CKE ................................................................................ 119
Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 119
Differential AC and DC Input Levels ................................................................................................ 123
CK/CK# and DQS/DQS# Time Requirements Before Ringback ( t DVAC) ............................................ 124
Single-Ended Levels for CK, CK#, DQS, DQS# .................................................................................. 125
Crosspoint Voltage for Differential Input Signals (CK, CK#, DQS, DQS#) ........................................... 126
Differential Input Slew Rate Definition ............................................................................................ 127
Single-Ended AC and DC Output Levels .......................................................................................... 127
Differential AC and DC Output Levels ............................................................................................. 128
Single-Ended Output Slew Rate Definition ...................................................................................... 128
Single-Ended Output Slew Rate ...................................................................................................... 128
Differential Output Slew Rate Definition ......................................................................................... 129
Differential Output Slew Rate ......................................................................................................... 129
AC Overshoot/Undershoot Specification ......................................................................................... 130
Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 132
Output Driver Sensitivity Definition ................................................................................................ 133
Output Driver Temperature and Voltage Sensitivity ......................................................................... 133
Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 133
I-V Curves ..................................................................................................................................... 134
Definitions and Calculations .......................................................................................................... 137
t CK(abs), t CH(abs), and t CL(abs) Definitions ................................................................................... 138
Refresh Requirement Parameters (Per Density) ............................................................................... 141
AC Timing ..................................................................................................................................... 142
CA and CS# Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ............................................ 150
CA and CS# Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ............................................ 150
Derating Values for AC/DC-Based t IS/ t IH (AC220) ........................................................................... 150
Derating Values for AC/DC-Based t IS/ t IH (AC300) ........................................................................... 151
Required Time for Valid Transition – t VAC > V IH(AC) and < V IL(AC) ....................................................... 151
Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) ....................................................... 156
Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) ....................................................... 157
Derating Values for AC/DC-Based t DS/ t DH (AC220) ........................................................................ 157
Derating Values for AC/DC-Based t DS/ t DH (AC300) ........................................................................ 157
Required Time for Valid Transition – t VAC > V IH(AC) or < V IL(AC) ......................................................... 158
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
相关PDF资料
PDF描述
IDT71V67803S133BQG8 IC SRAM 9MBIT 133MHZ 165FBGA
IDT71V65803S150PFG IC SRAM 9MBIT 150MHZ 100TQFP
IDT71V67903S85BQI8 IC SRAM 9MBIT 85NS 165FBGA
IDT71V67903S80BQI8 IC SRAM 9MBIT 80NS 165FBGA
IDT71V67903S75BQI8 IC SRAM 9MBIT 75NS 165FBGA
相关代理商/技术参数
参数描述