参数资料
型号: MT42L64M32D1KL-25 IT:A
厂商: Micron Technology Inc
文件页数: 66/164页
文件大小: 0K
描述: IC DDR2 SDRAM 2GBIT 168FBGA
标准包装: 1,000
格式 - 存储器: RAM
存储器类型: 移动 LPDDR2 SDRAM
存储容量: 2G(64M x 32)
速度: 400MHz
接口: 并联
电源电压: 1.14 V ~ 1.3 V
工作温度: -25°C ~ 85°C
封装/外壳: 168-WFBGA
供应商设备封装: 168-FBGA(12x12)
包装: 散装
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
BURST TERMINATE Command
? The 4-bit prefetch architecture enables BST command assertion on even clock cycles
following a WRITE or READ command. The effective burst length of a READ or WRITE
command truncated by a BST command is thus an integer multiple of four.
Figure 44: Burst WRITE Truncated by BST – WL = 1, BL = 16
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
WL = 1
CA[9:0]
Bank m
col addr a Col addr a
CMD
WRITE
NOP
NOP
NOP
BST
NOP
NOP
NOP
NOP
WL × t CK + t DQSS
DQS#
DQS
DQ
D IN A0
D IN A1
D IN A2
D IN A3
D IN A4
D IN A5
D IN A6
D IN A7
BST prohibited
Transitioning data
Notes:
1. The BST command truncates an ongoing WRITE burst WL × t CK + t DQSS after the rising
edge of the clock where the BST command is issued.
2. BST can only be issued an even number of clock cycles after the WRITE command.
3. Additional BST commands are not supported after T4 and must not be issued until after
the next READ or WRITE command.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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