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参数资料
| 型号： | MT42L64M32D1KL-25 IT:A |
| 厂商： | Micron Technology Inc |
| 文件页数： | 5/164页 |
| 文件大小： | 0K |
| 描述： | IC DDR2 SDRAM 2GBIT 168FBGA |
| 标准包装： | 1,000 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 LPDDR2 SDRAM |
| 存储容量： | 2G（64M x 32） |
| 速度： | 400MHz |
| 接口： | 并联 |
| 电源电压： | 1.14 V ~ 1.3 V |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 168-WFBGA |
| 供应商设备封装： | 168-FBGA（12x12） |
| 包装： | 散装 |
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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Input/Output Capacitance ......................................................................................................................... 113
Electrical Specifications – I DD Specifications and Conditions ........................................................................... 114
AC and DC Operating Conditions ................................................................................................................... 117
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 119
V REF Tolerances ......................................................................................................................................... 120
Input Signal .............................................................................................................................................. 121
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 123
Single-Ended Requirements for Differential Signals .................................................................................... 124
Differential Input Crosspoint Voltage ......................................................................................................... 126
Input Slew Rate ......................................................................................................................................... 127
Output Characteristics and Operating Conditions ........................................................................................... 127
Single-Ended Output Slew Rate .................................................................................................................. 128
Differential Output Slew Rate ..................................................................................................................... 129
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 131
Output Driver Impedance .............................................................................................................................. 131
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 132
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 133
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 133
Clock Specification ........................................................................................................................................ 137
t CK(abs), t CH(abs), and t CL(abs) ................................................................................................................ 138
Clock Period Jitter .......................................................................................................................................... 138
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 138
Cycle Time Derating for Core Timing Parameters ........................................................................................ 139
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 139
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 139
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 139
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 140
Refresh Requirements .................................................................................................................................... 141
AC Timing ..................................................................................................................................................... 142
CA and CS# Setup, Hold, and Derating ........................................................................................................... 149
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 156
Revision History ............................................................................................................................................ 163
Rev. N, Production – 3/12 ........................................................................................................................... 163
Rev. M, Production – 10/11 ........................................................................................................................ 163
Rev. L, Production – 09/11 .......................................................................................................................... 163
Rev. K, Production – 08/11 ......................................................................................................................... 163
Rev. J, Production – 05/11 .......................................................................................................................... 163
Rev. H, Production – 3/11 ........................................................................................................................... 163
Rev. G, Production – 1/11 ........................................................................................................................... 163
Rev. F, Advance – 11/10 .............................................................................................................................. 163
Rev. E, Advance – 09/10 .............................................................................................................................. 163
Rev. D, Advance – 07/10 ............................................................................................................................. 163
Rev. C, Advance – 07/10 ............................................................................................................................. 164
Rev. B, Advance – 03/10 .............................................................................................................................. 164
Rev. A, Advance – 03/10 .............................................................................................................................. 164
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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