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参数资料
| 型号： | MT46V32M16BN-5BLIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件页数： | 10/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16BN-5BLIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
18
2000 Micron Technology, Inc. All rights reserved.
for each burst type in “Operations” on page 19. The
user must not issue another command to the same
bank until the precharge time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate read bursts (with auto precharge disabled). The
most recently registered READ command prior to the
BURST TERMINATE command will be truncated, as
shown in “Operations” on page 19. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the DDR SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) refresh in FPM/EDO DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required. All banks must be idle before an
AUTO REFRESH command is issued.
The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 512Mb
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.8125s (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command
and the next AUTO REFRESH command is 9 x 7.8125s
(70.3s). Note the JEDEC specifications only allows 8 x
7.8125s, thus the Micron specification exceeds the
JEDEC requirement by one clock. This maximum
absolute interval is to allow future support for DLL
updates internal to the DDR SDRAM to be restricted to
AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
Although not a JEDEC requirement, to provide for
future functionality features, CKE must be active
(HIGH) during the AUTO REFRESH period. The AUTO
REFRESH period begins when the AUTO REFRESH
command is registered and ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). The DLL is automatically disabled upon enter-
ing SELF REFRESH and is automatically enabled upon
exiting SELF REFRESH (A DLL reset and 200 clock
cycles must then occur before a READ command can
be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. VREF voltage is also required for
the full duration of SELF REFRESH.
The procedure for exiting self refresh requires a
sequence of commands. First, CK and CK# must be
stable prior to CKE going back HIGH. Once CKE is
HIGH, the DDR SDRAM must have NOP commands
issued for tXSNR because time is required for the com-
pletion of any internal refresh in progress. A simple
algorithm for meeting both refresh and DLL require-
ments is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
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