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参数资料
| 型号： | MT46V32M16BN-5BLIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件页数： | 22/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16BN-5BLIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
29
2000 Micron Technology, Inc. All rights reserved.
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 20.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst and after the
tWR time.
NOTE:
For the WRITE commands used in the
following illustrations, auto precharge is
disabled.
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write pream-
ble; the LOW state on DQS following the last data-in
element is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 per-
cent to 125 percent of one clock cycle). All of the
WRITE diagrams show the nominal case, and where
the two extreme cases (i.e., tDQSS [MIN] and tDQSS
[MAX]) might not be
intuitive, they have also been
included. Figure 21 on page 30 shows the nominal
case and the extremes of tDQSS for a burst of 4.
Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain
High-Z and any additional input data will be
ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from
the new burst is applied after either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new WRITE
command should be issued x cycles after the first
WRITE command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture).
Figure 22 on page 31 shows concatenated bursts of
4. An example of nonconsecutive WRITEs is shown in
Figure 23 on page 32. Full-speed random write
accesses within a page or pages can be performed as
shown in Figure 24 on page 33.
Figure 20: WRITE Command
Data for any WRITE burst may be followed by a sub-
sequent READ command. To follow a WRITE without
truncating the WRITE burst, tWTR should be met, as
shown in Figure 25 on page 34.
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 26 on
Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal
array, and any subsequent data-in should be masked
with DM, as shown in Figure 27 on page 36.
Data for any WRITE burst may be followed by a sub-
sequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst, tWR should be
me,t as shown in Figure 28 on page 37.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in
that only the data-in pairs that are registered prior to
the tWR period are written to the internal array, and
any subsequent data-in should be masked with DM as
command, a subsequent command to the same bank
cannot be issued until tRP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
x8: A12
x16: A11, A12
x4: A0–A9, A11, A12
x8: A0–A9, A11
x16: A0–A9
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