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参数资料
| 型号： | MT46V32M16BN-5BLIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件页数： | 5/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16BN-5BLIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
13
2000 Micron Technology, Inc. All rights reserved.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 7. The burst length deter-
mines the maximum number of column locations that
can be accessed for a given READ or WRITE command.
Burst lengths of 2, 4, or 8 locations are available for
both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 3, Burst
Figure 7: Mode Register Definition
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3 (DDR400 Only)
Reserved
2.5
Reserved
Burst Length
CAS Latency BT
0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
Operating Mode
A10
A12 A11
BA0
BA1
10
11
12
13
0*
14
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
-
0
-
0
-
0
-
0
-
Valid
-
M6-M0
M8 M7
M9
M10
M12 M11
Burst Length
Reserved
2
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
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