参数资料
型号: MT46V32M16BN-5BLIT
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, 0.7 ns, PBGA60
封装: 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60
文件页数: 30/82页
文件大小: 2855K
代理商: MT46V32M16BN-5BLIT
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
36
2000 Micron Technology, Inc. All rights reserved.
Figure 27: WRITE to READ – Odd Number of Data, Interrupting
NOTE:
1. DI b = data-in for column b, DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask
these data elements.
tDQSS (NOM)
CK
CK#
COMMAND
WRITE
NOP
ADDRESS
Bank a,
Col b
Bank a,
Col n
READ
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
T6n
T5n
tWTR
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS (MIN)
CL = 2
DQ
DQS
DM
DI
b
DO
n
tDQSS (MAX)
CL = 2
DQ
DQS
DM
DI
b
DO
n
DON’T CARE
TRANSITIONING DATA
tDQSS
T3n
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