参数资料
型号: MT46V32M16BN-5BLIT
元件分类: DRAM
英文描述: 32M X 16 DDR DRAM, 0.7 ns, PBGA60
封装: 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60
文件页数: 39/82页
文件大小: 2855K
代理商: MT46V32M16BN-5BLIT
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
44
2000 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSNR has been met (if the pre-
vious state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the com-
mands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet ter
minated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated
Read with Auto
Precharge Enabled:
See following text – 3a, 3b, and 3c
Write with Auto
Precharge Enabled:
See following text – 3a, 3b, and 3c
3a.
The read with auto precharge enabled or write with auto precharge enabled states can
each be broken into two parts: the access period and the precharge period. For read with
auto precharge, the precharge period is defined as if the same burst was executed with auto
precharge disabled and then followed with the earliest possible PRECHARGE command that
Table 9:
Truth Table – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMAND/ACTION
NOTES
Any
HX
X
DESELECT (NOP/continue previous operation)
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
XX
X
Any Command Otherwise Allowed to Bank m
Row
Activating,
Active, or
Precharging
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7
LL
H
L
PRECHARGE
Read
(Auto-
Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7, 9
LL
H
L
PRECHARGE
Write
(Auto-
Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 8
LH
L
WRITE (select column and start new WRITE burst)
7
LL
H
L
PRECHARGE
Read
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7, 3a
LH
L
WRITE (select column and start WRITE burst)
7, 9, 3a
LL
H
L
PRECHARGE
Write
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 3a
LH
L
WRITE (select column and start new WRITE burst)
7, 3a
LL
H
L
PRECHARGE
相关PDF资料
PDF描述
MT46V32M81AZ4-6T:G 32M X 4 DDR DRAM, 0.75 ns, PDSO66
MT47H128M8HV-187ELIT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
MT48LC32M4A2P-7ELIT:G 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
相关代理商/技术参数
参数描述