- 您现在的位置：买卖IC网 > PDF目录224505 > MT46V32M16BN-5BLIT 32M X 16 DDR DRAM, 0.7 ns, PBGA60 PDF资料下载
参数资料
| 型号： | MT46V32M16BN-5BLIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件页数： | 51/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16BN-5BLIT |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页
512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
55
2000 Micron Technology, Inc. All rights reserved.
Table 21:
IDD Specifications and Conditions (x16; -6/-6T/-75E/-75Z/-75)
0°C
≤ T
A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V
Notes: 1–5, 10, 12, 14, 46; notes appear on page 61–64; See also Table 22, IDD Test Cycle Times, on page 56
MAX
PARAMETER/CONDITION
SYMBOL
-6/6T
-75E
-75Z/-75
UNITS
NOTES
OPERATING CURRENT: One bank; Active-Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0
130
115
mA
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
IDD1
160
145
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDD2P
5
mA
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock
cycle. VIN = VREF for DQ, DQS,
and DM
IDD2F
45
40
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One bank
active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
35
30
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active
; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
IDD3N
50
45
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN);
IOUT = 0mA
IDD4R
165
145
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once
per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
IDD4W
195
160
135
mA
AUTO REFRESH BURST CURRENT:
tREFC =tRC(MIN)
IDD5
290
280
mA
tREFC= 7.8us,
IDD5A
10
mA
SELF REFRESH CURRENT: CKE
≤ 0.2V
Standard
IDD6
55
5
mA
Low Power (L)
IDD6A
33
3
mA
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed;
tCK = tCK (MIN); Address and control inputs change only
during Active READ, or WRITE commands
IDD7
405
400
350
mA
相关PDF资料 |
PDF描述 |
|---|---|
| MT46V32M81AZ4-6T:G | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
相关代理商/技术参数 |
参数描述 |
|---|
发布紧急采购，3分钟左右您将得到回复。