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参数资料
| 型号： | MT46V32M16BN-5BLIT |
| 元件分类： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 0.7 ns, PBGA60 |
| 封装： | 10 X 12.50 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件页数： | 38/82页 |
| 文件大小： | 2855K |
| 代理商： | MT46V32M16BN-5BLIT |
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512Mb: x4, x8, x16
DDR SDRAM
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. H 7/04 EN
43
2000 Micron Technology, Inc. All rights reserved.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must
be applied on each positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when tRFC is met.
Once tRFC is met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode
Register:
Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include Reads or Writes with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be
used to end the READ burst prior to asserting a WRITE command.
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