参数资料
型号: TSB12LV26PZ
厂商: Texas Instruments, Inc.
英文描述: OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
中文描述: OHCI的山猫基于PCI的1394主控制器
文件页数: 23/106页
文件大小: 605K
代理商: TSB12LV26PZ
2
7
BIT
NUMBER
DESCRIPTION
DIR
FUNCTION
BIT NAME
9
ENA_
INSERT_IDLE
Insert Idle
Enable
R/W
Per P1394a, the link is required to insert an idle state on the
control lines after the Phy grants the link control of the
Phy/link interface. If using a P1394a Phy, this bit should be
set to 1 in order for the link to drive an idle state following the
grant state from the Phy. For 1394-1995 Phys this bit must
remain low.
10
RSTTX
Transmitter
Reset
R/W
When RSTTX is set, the entire transmitter resets
synchronously. This bit clears itself.
11
RSTRX
Receiver
Reset
R/W
When RSTRX is set, the entire receiver resets
synchronously. This bit clears itself.
12
CTNDRSTAT
Contenter
status
R/W
Contender status. On power up, this bit reflects the status of
the CONTNDR pin. When bit 13, CTNDRISIN, is 0 this bit
will be driven out to the CONTNDR pin. If CTNDRISIN is 1
this bit is not used. (Only use on 1394
1995 Phys, or
P1394a Phys when using hardware reset, otherwise, use
the 1394a Phy registers to set the nodes contender status).
13
CTNDRISIN
Contender
Driver Enable
R/W
Driver enable for the CONTNDR pin. On power up this bit is
set to 1 which disables the driver and allows reading of the
state of the CONTNDR pin. Writing a 0 to this bit will enable
the driver and will drive bit 12, CTNDRSTAT, to the
CONTNDR pin.
14
RESERVED
Reserved
15
BUSNRST
Bus number
reset enable
R/W
When this enable is set to high, the bus number field clears
to 3FFh when a local bus reset is received.
16
17
BDIV0, BDIV1
BCLK divisor
encode bits
R/W
BCLK divisors encode bits. Used to divide down the BCLK
to generate the link power status (LPS) clock to the Phy.
BDIV0
0
BDIV1
0
DESCRIPTION
Divide by 16. Default power on value.
Recommended for BCLK frequencies in
the range of 8
88 MHz.
0
1
Divide by 2. Recommended for BCLK
frequencies in the range of 1
11 MHz.
1
0
Divide by 4. Recommended for BCLK
frequencies in the range of 2
22 MHz.
1
1
Divide by 32. Recommended for BCLK
frequencies in the range of 16
176
MHz
18
DMACKCOMP
Data Mover
Acknowledge
Complete
R/W
Data mover acknowledge complete. This bit controls the
acknowledge response to an asynchronous packet
received and routed to the DM port. The default and power
on value is 0 which means to respond with ack pending. A 1
means to respond with an ack complete for write request
packets.
19
FIFOACKCOMP
FIFO
Acknowledge
Complete
R/W
FIFO acknowledge complete. This bit controls the
acknowledge response to an asynchronous packet
received and routed to the GRF. The default and power on
value is 0 which means to respond with ack pending. A 1
means to respond with ack complete.
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