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| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 44/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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3
–
7
3.3.2
Byte and word fixed-timing reads shown in Figure 3
–
7 and Figure 3
–
8. Fixed-timing mode supports burst
transfers. If MCS is asserted low for more than one BCLK cycle, burst mode is enabled. The fixed-timing
burst mode does not have a limit on the maximum burst size allowed.
Microcontroller Fixed-Timing Mode
The timing sequence in the fixed-timing a read transaction can be summarized as follows:
1.
The host pulses MCS low to signal the start of access. Pulsing MCS low for more than once clock
cycle will enable burst mode. The number of BCLK cycles during which MCS is asserted low
determines the burst size.
2.
When the rising edge of BCLK samples MCS low and MWR high, the register value or GRF data
pointed to by MA is latched onto the MD lines. The MD lines will latch on every rising edge of BCLK
if MCS is asserted low.
3.
After 2 BCLK cycles, the TSB12LV32 pulses MCA low for one clock cycle to signal the completion
of the requested operation. If MCS is pulsed low for
n
BCLK cycles, MCA will also be pulsed low
for
n
cycles. Note that MA needs only contain valid data during the first cycle in which MCS is low.
Except for the first one, every data transfer takes only one BCLK cycle. If a read transaction is
accessing the CFR, it may not cross any register boundary.
Another read or write transaction can begin after the next rising edge of BCLK. Note that data size is
determined by the MCMODE/SIZ1 and M8BIT/SIZ0 signals. The ColdFire signal is only asserted high when
the micro interface is operating in ColdFire mode.
BCLK
COLDFIRE
M8BIT/SIZ0
MCMODE/SIZ1
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A1
A2
D1
D2
D3
D4
D5
Figure 3
–
7. Byte Fixed-Timing Read
相关PDF资料 |
PDF描述 |
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| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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