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| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 72/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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5
–
16
5.2.7
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations is performed:
Asynchronous Packet Receive With Headers and Trailer
Step 1:
The packet router control logic will route the packet to the data mover. At the same time
DMDONE will be asserted high for one DMCLK cycle.
Step 2:
This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only
asserted high when the header quadlets are being received.
Step 3:
After all the data payload has been received on the DMD[0:15] lines, PKTFLAG will be
asserted high again as the trailer quadlet is being received. Once the entire packet is
received, the DMRW line will be asserted low.
Figure 5
–
25 and Figure 5
–
26 show the timing diagram for this mode for the quadlet receive and the block
receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5
–
26
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
–
25. Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
–
26. Asynchronous Block Receive With Headers and Trailer at 400 Mbps
5.2.8
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations are performed:
Asynchronous Packet Receive Without Headers and Trailer
Step 1:
The packet router control logic will route the packet to the data mover. After the headers
are sent through, DMDONE will be asserted high for one DMCLK cycle.
Step 2:
DMRW is then asserted high as the data payload comes through.
Step 3:
After all data has been received on the DMD[0:15] lines, DMRW will be asserted low and
the trailer quadlet will then come out on the DMD[0:15] lines.
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| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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