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参数资料
| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 49/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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3
–
12
3.3.3
The TSB12LV32 supports a glueless interface to the ColdFire family of microcontrollers. To enable this
mode, the ColdFire pin must be asserted and kept high for the entire access cycle. The timing diagram for
a ColdFire read operation is shown in Figure 3
–
13.
The timing sequence for a ColdFire read access can be summarized as follows:
1.
The ColdFire pulses MCS low for one BCLK cycle to signal the start of access.MCS must only
be asserted for one clock cycle.
2.
When the rising edge of BCLK samples MCS low and MWR high, MD lines are enabled, but do
not yet contain valid data. The MA lines should contain the address information at this point. MA
is only required to be available for one BCLK cycle. The data transfer size is determined by the
state of the MCMODE/SIZ1 and M8BIT/SIZ0 lines.
3.
The TSB12LV32 pulses MCA low for n clock cycles to signal the requested operation is complete.
The number n depends on the data transfer size specified by the MCMODE/SIZ1 and
M8BIT/SIZ0 lines. The CFR register value or GRF memory data pointed to by the MA lines is
latched onto the MD lines. MCA will pulse for one clock cycle on every word (2-Bytes) transfer.
The microinterface does burst transfers if the MCMODE/SIZ1 and M8BIT/SIZ0 lines indicate more than
2-bytes (1 word) of data. The TSB12LV32 does not support 1-byte transfers in the ColdFire mode. If a
transfer error condition occurs, TEA will be asserted low for one BCLK cycle. An error condition can occur
if the MCMODE/SIZ1 and M8BIT/SIZ0 lines specify a transfer size of 1-byte or if their state changes during
the access cycle. Note that all 16-bits of the MD lines are always used in this mode.
Microcontroller ColdFire Mode
BCLK
COLDFIRE
MCMODE/SIZ1
M8BIT/SIZ0
MWR
MCS
MCA
MA[0:6]
MD[0:7]
MD[8:15]
A1
A2
D2
D6
A3
D1
D3
D4
D5
Figure 3
–
13. ColdFire Read
The ColdFire write transaction is shown in Figure 3
–
14. Unlike the handshake and fixed-timing write modes,
the ColdFire write operation requires the data on the MD lines be available one BCLK cycle after the address
on the MA lines is sampled. Violating this timing requirement may result in a transfer error, causing TEA to
be asserted low for one BCLK cycle.
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相关代理商/技术参数 |
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|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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