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参数资料
| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 30/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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2
–
14
2.2.8
Diagnostic Register at 20h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
29 30 31
28
B
B
B
B
B
B
R
R
B
B
STATESEL0
STATESEL1
STATESEL2
The power-up reset value of this register =
0000_4AD0
’
h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
B0_BUSY
Byte 0 busy
R
Byte 0 busy. When this bit is set, no microinterface write to byte 0 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 0.
1
B1_BUSY
Byte 1 busy
R
Byte 1 busy. When this bit is set, no microinterface write to byte 1 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 1.
2
B2_BUSY
Byte 2 busy
R
Byte 2 busy. When this bit is set, no microinterface write to byte 2 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 2.
3
B3_BUSY
Byte 3 busy
R
Byte 3 busy. When this bit is set, no microinterface write to byte 3 of
any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 3.
4
B0_PND
Byte 0
pending
R
Byte 0 pending. When this bit is set, it indicates that byte 0 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
5
B1_PND
Byte 1
pending
R
Byte 1 pending. When this bit is set, it indicates that byte 1 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
6
B2_PND
Byte 2
pending
R
Byte 2 pending. When this bit is set, it indicates that byte 2 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.
7
B3_PND
Byte 3
pending
R
Byte 3 pending. When this bit is set, it indicates that byte 3 of a word
or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete
this bit will be cleared.
8
RAM_TEST
R/W
This bit can be set only when TESTMODE is high. When this bit is
set, the built in self test(BIST) for the FIFOs (transmit and receive)
will be run. On completion of the test hardware will reset this bit to 0
and simultaneously set bit 30 and 31.
9
REGRW
Register
read/write
access
R/W
When REGRW is set, write-protected bits in various registers can
be written to.
10
–
15
RESERVED
Reserved
16
–
19
STATSEL0
State0
select
R/W
Status output select bits. Used to program the output of STAT0
terminal. See table in
Operation
section.
20
–
23
STATSEL1
State1
select
R/W
Status output select bits. Used to program the output of STAT1
terminal. See table in
Operation
section.
24
–
27
STATSEL2
State2
select
R/W
Status output select bits. Used to program the output of STAT2
terminal. See table in Operation section.
28
–
31
RESERVED
Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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