参数资料
型号: TSB12LV26PZ
厂商: Texas Instruments, Inc.
英文描述: OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
中文描述: OHCI的山猫基于PCI的1394主控制器
文件页数: 65/106页
文件大小: 605K
代理商: TSB12LV26PZ
5
9
5.1.4.1
In this mode, the header information is first loaded into the header0
header3 registers through the
microcontroller interface. The headers will subsequently be automatically inserted into the data once the
data mover starts streaming it through to the link core transmitter logic. The following steps further illustrate
the process:
Asynchronous Packet Transmit With Automatic Header Insertion
Step 1:
Asynchronous header quadlets (3 quadlets in quadlet receive mode and 4 quadlets in block
receive mode) are loaded into header0
header3 registers through a write operation from
the microcontroller interface. Loading one header requires a single write operation.
Step 2:
Header quadlets are forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Asynchronous packet is sent to the 1394 bus through the Phy.
NOTE:
The data coming through the data mover port is typically supplied by an external
fast memory block (i.e., FIFO, DRAM). This external memory logic may begin
transmitting data through to the data mover port exactly one DMCLK cycle after the
DMPRE output pin on the GP2Lynx is asserted high.
CFR REGISTER
Step 4
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Quadlet#0
Packet sent
to 1394 bus
through the
Phy
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Loaded only in
Block Receive
Data
Mover
Port
Step 3 (packet data)
Step 2
Step 3
Step 1
Headers
loaded
Micro-
controller
Interface
Step 1
Write
Header
Quadlets
Figure 5
11. Asynchronous Transmit With Auto Header Insertion
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