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| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 83/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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7
–
5
Table 7
–
3. Quadlet
–
Receive Format Functions
FIELD NAME
DESCRIPTION
numofQuadlets
Total number of quadlets in the current packet (payload and header quadlets only).
ackCode
This 5-bit field holds the acknowledge code sent by the receiver for the current packet (see
Table 6-13 in the draft standard).
Spd
The spd field indicates the speed at which the current packet was sent. 00 = 100 Mbits/s,
01 =200 Mbits/s, 10 = 400 Mbits/s, and 11 is undefined for this implementation.
destinationID
The destinationID field contains the concatenation of the 10-bit bus number and the 6-bit
node number that forms the node address to which the current packet is being sent.
tLabel
The tLabel field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This field is used to pair up a response packet with its corresponding
request packet.
rt
The rt field is the retry code for the current packet is 00 = new, 01 = retry_X, 10 = retryA, and
11 = retryB.
tCode
The tCode field is the transaction code for the current packet (see Table 6-10 of the
IEEE
–
1394 standard).
priority
The priority field contains the priority level for the current packet. For cable implementation,
the value of the bits must be zero (for backplane implementation, see clause 5.4.1.3 and
5.4.2.1 of the IEEE
–
1394 standard).
sourceID
The sourceID field contains the node ID of the sender of the current packet.
destination OffsetHigh,
destination OffsetLow
The concatenation of the destination OffsetHigh and the destination OffsetLow fields ad-
dresses a quadlet in the destination nodes address space. This address must be quadlet
aligned (modulo 4). (The upper four bits of the destination OffsetHigh field are used as the
response code for lock-response packets, and the remaining bits are reserved.)
quadlet data
For write requests and read responses, the quadlet data field holds the transferred data. For
write responses and read requests, this field is not present.
7.1.4
The block-receive format through the FIFO is shown in Figure 7-6 and is described in Table 7-5. The first
16 bits of the first quadlet contain the node and bus ID of the destination node, and the last 16 bits contain
packet-control information. The first 16 bits of the second quadlet contain the node and bus ID of the source
node, and the last 16 bits of the second quadlet and all of the third quadlet contain the 48-bit, quadlet-aligned
destination offset address. All remaining quadlets, except for the last one, contain data that is used only for
write requests and read responses. For block read requests and block write responses, the data field is
omitted. The last quadlet contains packet-reception status.
Block Receive
3
2
1
0
7
6
5
4
11
10
9
8
15
14
13
12
19
18
17
16
20 21
31
30
29
28
27
26
25
24
23
22
spd
numofQuadlets
sourceID
destinationOffsetHigh
0
0
0
0
0
ackCode
0
0
0
0
0
0
prioity
tCode
rt
tLabel
destinationID
destinationOffsetLow
dataLength
block data (if any)
extended_tCode
Figure 7
–
6. FIFO Block-Receive Format
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相关代理商/技术参数 |
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| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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