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| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 55/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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4
–
2
4.4
The cycle timer is only used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined by the IEEE 1394
–
1995 specification. In the TSB12LV32, the cycle-timer register is implemented
in the cycle timer located in the IEEE-1212 initial register space at location 200h and can also be accessed
through the local bus at TSB12LV32 CFR address 14h. The low-order 12 bits of the timer are a modulo 3072
counter, which increments once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order
bits are a count of 8,000-Hz (or 125-
μ
s) cycles, and the highest 7 bits count seconds. The cycle timer
contains the cycle-timer register. The cycle-timer register consists of three fields: cycle offset, cycle count,
and seconds count. The cycle timer has two possible sources. First, when the cycle source (CYSRC) bit
in the configuration register (bit 21 at 08h) is set, then the CYCLEIN input causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is the cycle master. The timer can also be disabled using
the cycle-timer-enable bit (CYTEN) in the control register. The second cycle-source option is when the
CYSRC bit is cleared. In this state, the cycle-offset field of the cycle-timer register is incremented by the
internal 24.576-MHz clock. The cycle timer is updated by the reception of the cycle-start packet for the
non-cycle master nodes. The cycle-offset field in the cycle-start packet is used by the cycle-master node
to keep all nodes in phase and running with a nominal isochronous cycle of 125
μ
s. The cycle-start bit is
set when the cycle-start packet is sent from the cycle master node or received by a noncycle master node.
Cycle Timer
4.5
The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cyclemaster bit (CYMAS) is set in the control register.
Cycle Monitor
4.6
The CRC module generates a 32-bit CRC for error detection. This is done for both the header and the data.
The CRC module generates the header and data CRC for transmitting packets and checks the header and
data CRC for received packets (see the IEEE-1394
–
1995 standard for details on the generation of the CRC).
Cyclic Redundancy Check (CRC)
4.7
Asynchronous and Isochronous receive packets will be routed to the DM port or the GRF via the receiver
routing control logic. Any asynchronous packet addressed in the range of 0 to 0000_FFFF_FFFF and is of
the
write request
type will be routed to the DM port according to Table 4
–
1. When bit IRCVALL (at 18h) is
set, all isochronous data will be routed according to Table 4
–
1. Note that self-ID packets and Phy packets
are always received by the GRF regardless of the routing control settings.
Packet Routing Control Logic
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| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
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| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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