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参数资料
| 型号： | TSB12LV26PZ |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山猫基于PCI的1394主控制器 |
| 文件页数： | 77/106页 |
| 文件大小： | 605K |
| 代理商： | TSB12LV26PZ |
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6
–
2
Step 2:
Writing the next (n-1) quadlets of the packet:
a)
Write the first 8-bits of each quadlet to ATF location 54h.
b)
Write the second 8-bits of each quadlet to ATF location 55h.
c)
Write the third 8-bits of each quadlet to ATF location 56h.
d)
Write the fourth 8-bits of each quadlet to ATF location 57h.
The data is not yet confirmed for transmission.
Last (N
th
) quadlet of the packet:
a)
Write the first 8-bits of the quadlet to ATF location 58h.
b)
Write the second 8-bits of the quadlet to ATF location 59h.
c)
Write the third 8-bits of the quadlet to ATF location 5Ah.
d)
Write the fourth 8-bits of the quadlet to ATF location 5Bh.
The data is now confirmed for transmission.
To write to the ATF in a word fashion, the following steps should be followed:
Step 1:
Writing the first quadlet of the packet:
a)
Write the first 16-bits of the quadlet to ATF location 50h.
b)
Write the second 16-bits of the quadlet to ATF location 52h.
The data is not yet confirmed for transmission.
Step 2:
Writing the next (n-1) quadlets of the packet:
a)
Write the first 16-bits of each quadlet to ATF location 54h.
b)
Write the second 16-bits of each quadlet to ATF location 56h.
The data is not yet confirmed for transmission.
Step 3:
Last (N
th
) quadlet of the packet:
a)
Write the first 16-bits of the quadlet to ATF location 58h.
b)
Write the second 16-bits of the quadlet to ATF location 5Ah.
The data is now confirmed for transmission.
All writes to the ATF must be quadlet aligned (i.e., only an even number of write accesses is allowed). If the
first quadlet of a packet is not written to the ATF_First location, the transmitter enters a state denoted by an
ATStuck interrupt. An underflow of the ATF also causes an ATSTK interrupt. When this state is entered, no
asynchronous packets can be sent until the ATF is cleared by way of the ATFCLR control bit (bit 0 at CFR
30h). However isochronous packets may still be sent while the ATF is in this state.
6.3
ATF Burst Access
It is allowable to perform a burst write into location 54h (ATF_Continue), which allows multiple quadlets to
load into ATF, but the data is not confirmed for transmission. It is also allowable to perform burst write to
location 58h (ATF_Continue & Update), which allows multiple quadlets to load into ATF, and the data is
confirmed for transmission. Write accesses to address 5Ch (ATF_Burst Write) writes the whole packet into
the ATF. The first quadlet written into ATF has the control bit set to 1 to indicate this is the first quadlet of
the packet, and the rest of the quadlets have the CD bit set to 0. The last quadlet written into ATF confirms
the packet for transmission.
To do a burst write operation the host bus master must continually drive MCS low. The TSB12LV32 loads
MD0
–
MD15 to the ATF during each rising edge of BCLK while MCS is low. At the same time it asserts MCA
(MCA is always one cycle behind MCS) low. The CD bit is 0 for ATF_Continue and ATF_Continue & Update.
The ATF_First_Update is a unique address location optimised for transmitting zero length isochronous
packets (including asynchronous streaming packets). A zero-length packet contains no data payload, and
only the packet header and header CRC are transmitted.
Step 3:
6.4
Access to the GRF is done with a read from the GRF, which requires a read from address 60h. The GRF
will accumulate self-ID packets upon bus-reset. All quadlets of a self-ID packet are saved in the GRF after
General-Receive-FIFO (GRF)
相关PDF资料 |
PDF描述 |
|---|---|
| TSB14AA1 | FPGA (Field-Programmable Gate Array) |
| TSB14AA1I | FPGA (Field-Programmable Gate Array) |
| TSB14AA1T | FPGA (Field-Programmable Gate Array) |
| TSB14C01MHV | IC APEX 20KE FPGA 160K 484-FBGA |
| TSB14C01HV | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSB12LV26PZT | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based Host Controller RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26PZTG4 | 功能描述:1394 接口集成电路 OHCI-Lynx PCI-Based IEEE1394 Host Cntrlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV26TPZEP | 功能描述:1394 接口集成电路 Mil Enh OHCI-Lynx IEEE 1394 Host Cntlr RoHS:否 制造商:Texas Instruments 类型:Link Layer Controller 工作电源电压: 封装 / 箱体:LQFP 封装:Tray |
| TSB12LV31 | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB12LV31PZ | 制造商:TI 制造商全称:Texas Instruments 功能描述:IEEE 1394-1995 General-Purpose Link-Layer Controller |
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