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参数资料
| 型号： | V59C1G01808QALF19E |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, BGA68 |
| 封装： | ROHS COMPLIANT, FBGA-68 |
| 文件页数： | 1/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1G01808QALF19E |
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1
V59C1G01(408/808/168)QA
HIGH PERFORMANCE 1Gbit DDR2 SDRAM
8 BANKS X 32Mbit X 4 (408)
8 BANKS X 16Mbit X 8 (808)
8 BANKS X 8Mbit X 16 (168)
PRELIMINARY
V59C1G01(408/808/168)QA Rev.1.3 June 2008
3
25A
25
19A
DDR2-667
DDR2-800
DDR2-1066
Clock Cycle Time (tCK3)
5ns
Clock Cycle Time (tCK4)
3.75ns
Clock Cycle Time (tCK5)
3ns
Clock Cycle Time (tCK6)
3ns
2.5ns
Clock Cycle Time (tCK7)
3ns
2.5ns
1.875ns
System Frequency (fCK max)
333 MHz
400 MHz
533 MHz
Features
■ High speed data transfer rates with system frequency
up to 533 MHz
■ 8 internal banks for concurrent operation
■ 4-bit prefetch architecture
■ Programmable CAS Latency: 3, 4 ,5 , 6 and 7
■ Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6
■ Write Latency=Read Latency-1
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length: 4 and 8
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase
between 0oC and 85oC
■ OCD (Off-Chip Driver Impendance Adjustment)
■ ODT (On-Die Termination)
■ Weak Strength Data-Output Driver Option
■ Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ DQS can be disabled for single-ended data strobe
■ Read Data Strobe (RDQS) supported (x8 only)
■ Differential clock inputs CK and CK
■ JEDEC Power Supply 1.8V ± 0.1V
■ VDDQ=1.8V ± 0.1V
■ Available in 68-ball FBGA for x4 and x8 component or
92-ball FBGA for x16 component
■ RoHS compliant
■ PASR Partial Array Self Refresh
■ tRAS lockout supported
Description
The V59C1G01(408/808/168)QA is a eight bank DDR
DRAM organized as 8 banks x 32Mbit x 4 (408), 8 banks x
16Mbit x 8 (808), or 8 banks x 8Mbit x 16 (168). The
V59C1G01(408/808/168)QA achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the eight memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
68 ball FBGA
92 ball FBGA
-3
-25A
-25
-19A
Std.
L
0°C to 85°C
Blank
Table 1:
Grade
CL
tRCD
tRP
Unit
-3 (DDR2-667)
5
CLK
-25A (DDR2-800)
6
CLK
-25 (DDR2-800)
5
CLK
-19A (DDR2-1066)
7
CLK
Available Speed Grade
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