- 您现在的位置：买卖IC网 > PDF目录202173 > V59C1G01808QALF19E (PROMOS TECHNOLOGIES INC) 128M X 8 DDR DRAM, BGA68 PDF资料下载
参数资料
| 型号： | V59C1G01808QALF19E |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, BGA68 |
| 封装： | ROHS COMPLIANT, FBGA-68 |
| 文件页数： | 17/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1G01808QALF19E |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
24
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a
wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write opera-
tion on successive clock cycles at data rates of up to 667Mb/sec/pin for main memory. The boundary of the
burst cycle is restricted to specific segments of the page length.
For example, the 32Mbit x 4 I/O x 8 Bank chip has a page length of 1 kByte (defined by CA0-CA9 & CA11).
In case of a 4-bit burst operation (burst length = 4) the page length of 1 kByte is divided into 512 uniquely
addressable segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512
segments (defined by CA0-CA8) beginning with the column address supplied to the device during the Read
or Write Command (CA0-CA9 & A11). The second, third and fourth access will also occur within this segment,
however, the burst order is a function of the starting address, and the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the page length of 1 kByte is divided into 256 uniquely
addressable double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of
the 256 double segments (defined by CA0-CA7) beginning with the column address supplied to the deivce
during the Read or Write Command ( CA0-CA9 & CA11).
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore
the minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles
.
For 8 bit burst operation (BL = 8 ) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation. For details see the “Burst Interrupt” - Section of this
datasheet.
Read Burst Timing Example : (CL = 3, AL = 0, RL = 3, BL = 4)
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T12
CMD
DQ
RB
DQS,
DQS
READ B
NOP
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3 Dout C0
Dout C1
Dout C2
Dout C3
NOP
READ C
tCCD
CK, CK
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1G01808QALF37E | 128M X 8 DDR DRAM, BGA68 |
| V59C1G01808QAUF37H | 128M X 8 DDR DRAM, PBGA68 |
| V59C1512804QALP19A | 64M X 8 DDR DRAM, PBGA68 |
| V59C1512804QAUF19AI | 64M X 8 DDR DRAM, PBGA68 |
| V59C1512804QAUP19AH | 64M X 8 DDR DRAM, PBGA68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V5A010CB | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER |
| V5A010CB | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER |
| V5A010CB4D | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
| V5A010CB4D | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
| V5A010CB4E | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
发布紧急采购，3分钟左右您将得到回复。