参数资料
型号: V59C1G01808QALF19E
厂商: PROMOS TECHNOLOGIES INC
元件分类: DRAM
英文描述: 128M X 8 DDR DRAM, BGA68
封装: ROHS COMPLIANT, FBGA-68
文件页数: 13/79页
文件大小: 1028K
代理商: V59C1G01808QALF19E
20
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
DC Electrical Characteristics and Operation Conditions:
Parameter / Condition
Symbol
min.
nom.
max.
Units
Notes
Rtt eff. impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt1(eff)
60
75
90
1
Rtt eff. impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt2(eff)
120
150
180
1
Deviation of VM with respect to VDDQ/2
delta VM
- 6
+ 6
%2
1) Measurement Definition for Rtt(eff):
Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively
Rtt(eff) = (VIHac - VILac) /( I(VIHac) - I(VILac))
2) Measurement Defintion for VM:
Measure voltage (VM) at test pin (midpoint) with no load:
delta VM =(( 2* VM / VDDQ) - 1 ) x 100%
Symbol
Parameter / Condition
min.
max.
Units
Notes
tAOND
ODT turn-on delay
2
tCK
tAON
ODT turn-on
tAC(min)
tAC(max) + 0.7ns
ns
1
tAONPD
ODT turn-on (Power-Down Modes)
tAC(min) + 2ns
2 tCK + tAC(max) + 1
ns
tAOFD
ODT turn-off delay
2.5
tCK
tAOF
ODT turn-off
tAC(min)
tAC(max) + 0.6ns
ns
2
tAOFPD
ODT turn-off (Power-Down Modes)
tAC(min) + 2ns
2.5 tCK + tAC(max) + 1ns
ns
tANPD
ODT to Power Down Mode Entry Latency
3
tCK
tAXPD
ODT Power Down Exit Latency
8
tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max. is when the ODT resistance is fully on. Both are measured from tAOND.
2) ODT turn off time min. is when the device stars to turn-off ODT resistance..
ODT turn off time max. is when the bus is in high impedance. Both are measured from tAOFD.
ohm
AC Electrical Characteristics and Operation Conditions: For speed 667/800
Rtt eff. impedance value for EMRS(A6,A2)=1,1; 50 ohm
Rtt3(eff)
50
ohm
1
40
60
2
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