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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 13/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
(approximately the spacing for a 16KSPS output sample rate
when using 65MSPS clock) using IWA = *00Ah bits 11:0.
The number and order of the filtering in the filter chain is defined
by a FIR control program. The FIR control program is a
sequence of up to 32 instruction words. Each instruction word
can be a filter or program flow instruction. The filter instruction
defines a FIR in the chain, specifying the type of FIR, number of
taps, decimation, memory allocation, etc. For program flow, a
wait for input sample(s) instruction, a loop counter load, and
several jumps (conditional and unconditional) are provided. The
HSP50216 evaluation board includes software for automatically
rate to the FIR from the CIC filter would be 2.5MSPS. The
impulse response length would be 38 μ sec (95 taps at
0.4 μ s/tap).
Each additional filter added to the signal processing chain
requires one instruction step. As an example of this, a typical
filter chain might consist of two decimate-by-2 halfband
filters being followed by a shaping filter with the final filter
being a resampling filter. The program for this case might be
(see Sample Filter Program #2 Program Instructions below):
SAMPLE FILTER #2 PROGRAM
generating FIR control programs for most filter requirements.
Examples of programs FIR control programs are given below.
The simplest filter program computes a single filter. It has
three instructions (see Sample Filter #1 Program Instructions
below):
SAMPLE FILTER #1 PROGRAM
STEP
0
1
INSTRUCTION
Wait for enough input samples (usually equal to the
total decimation -- 8 in this case)
FIR
Type = even symmetry
15 taps
Halfband
Decimate by 2
STEP
0
1
INSTRUCTION
Wait for enough input samples
(equal to the decimation factor)
FIR
Type = even symmetric
Compute four outputs
Memory block size 32
Memory block start at 0
Coefficient block start at 13
Output to step 2
Decrement wait count
95 taps
Decimate by 2
Compute one output
Decrement wait counter
Memory block size 128
Memory block start at 64,
Coefficient block start at 64
Step size 1
Output to AGC
2
FIR
Type = even symmetry
23 taps
Halfband
Decimate by 2
Compute two outputs
Memory block size 32
Memory block start at 32
Coefficient block start at 24
2
Jump, Unconditional, to step 0
Output to step 3
The parameters of the FIR (including type, number of taps,
decimation and memory usage) are specified in the bit fields
of the step 1 instruction word. To change the filtering the only
other change needed is the number of samples in the wait
threshold register (IWA = *00C, bits 9:0). The filter in this
example requires 52 clock cycles to compute, allocated as
follows:
SAMPLE FILTER #1 CLOCK CYCLES CALCULATION
3
FIR
Type = even symmetry
95 taps
Decimate by 2
Compute one output
Memory block size 128
Memory block start at 64
Coefficient block start at 64
Step size 1
Output to step 4
CLOCK
CYCLES
48
2
2
52
FUNCTION PERFORMED
Clocks for FIR computation (two taps/clock due to
symmetry)
Clocks for writing the input data into the data RAMs
(Decimate by 2 requires 2 inputs per output)
Clocks for the program flow instructions (wait and
jump)
Total
4
5
FIR
Type = resampler
Increment NCO
6 taps
Compute one output
Memory block size 8
Memory block starts at 192
Coefficient block start at 512
Step size 32
Output to AGC
Jump, Unconditional, to 0
Using a 65MSPS clock, the output sample rate could be as
high as 65MSPS/52 clocks = 1.25MSPS. The input sample
13
FN4557.6
August 17, 2007
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相关代理商/技术参数 |
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|---|---|
| HSP50306 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306_04 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-25 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50306SC-2596 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Digital QPSK Demodulator |
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