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| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 30/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
μ P Read/Write Procedures
To Write to the Internal Registers:
1. Load the indirect write holding registers at direct address
ADD(2:0) = 0 and 1 with the data for the internal register
(16 or 32 bits depending on the internal register being
addressed).
2. Write the Indirect Write Address of the internal register
being addressed to direct address ADD(2:0) = 2 (Note: A
write strobe to transfer the contents of the Indirect Write
Holding Register into the Target Register specified by the
Indirect Address will be generated internally).
3. Wait 4 clock cycles before performing the next write to the
indirect write holding registers.
To Write to the Internal Instruction/Coefficient
RAMs:
1. Put the filter compute engine of the desired channel into
the hold mode by setting bit 31 of the Filter Compute
Engine / Resampler Control register located at
IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3
depending on the channel being addressed). By setting
bit 31 all FIR processing for the channel addressed will be
stopped.
2. Load the indirect write holding registers at direct address
ADD(2:0) = 0 and 1 with the data for the internal RAM
location.
3. Write the Indirect Write Address of the internal RAM
location being addressed to direct address ADD(2:0) = 2
(Note: A write strobe to transfer the contents of the
Indirect Write Holding Register into the RAM location
specified by the Indirect Address will be generated
internally).
4. Wait 4 clock cycles before performing the next write to the
indirect write holding registers.
5. After all data has been loaded, set the μ PHold bit back
low.
To Read Internal Registers:
1. Write the Indirect Read Address of the internal register
being addressed to direct address ADD(2:0) = 3.
2. Perform a read of the Indirect Read Holding Registers at
direct address ADD(2:0) = 0 and 1.
To Read Data Outputs:
1. Set up the μ P FIFO Read Order Control Register (located
at Global Write Address (GWA) = F820h - F83Fh).
2. Wait for interrupt or check flag.
3. Data can then be read, 16 bits at a time, at direct
address 2, ADD(2:0) = 2.
4. Repeat step 3 for desired number of words.
5. Go to step 2.
To Read Instruction/Coefficient Values:
1. Put the filter compute engine of the desired channel into
the hold mode by setting bit 31 of the Filter Compute
Engine / Resampler Control register located at
30
IWA = *00Ah (Note: The * is equal to 0, 1, 2 or 3
depending on the channel being addressed).
2. Write the Indirect Read Address (IRA) of the internal
RAM/ROM location being addressed to direct address
ADD(2:0) = 3.
3. Wait 4 clock cycles.
4. Read the data at direct address ADD(2:0) = 0 and 1.
5. After all the data has been read, set the μ PHold bit back
low.
Recommended HSP50216 configuration
procedure following a hardware reset (i.e.
RESETb is pulsed low):
1. Load Global Write Address registers GWA F800 - GWA
F808 and GWA F820 - GWA F83F.
2. For each signal processing channel (0-3):
a. Set mPHold bit located at Indirect Write Address
register IWA *00A - 31.
b. Load Filter Compute Engine Instruction RAMS.
c. Load Filter Compute Engine Coefficient RAMS.
d. Load IWA registers *000 - *019. (Clear the mPHold bit
in register IWA *00A - 31).
e. Wait 32 clocks (CLK) for the reset to complete in the
Filter Compute Engine.
3. Generate a SYNCI to enable the input data or to
synchronize the processing to external events or
generate a SYNCO by writing to GWA F809.
NOTE: For the latter method, the SYNCO pin must be connected to
the SYNCI pin.
Recommended HSP50216 Channel
Reconfiguration Procedure:
1. Disable the serial output for the desired channel in
register GWA F801 - 3, 2, 1 or 0.
2. Disable the interrupts from the channel in register GWA
F802 - 31, 23, 15, or 7.
3. Set the mPHold bit in register IWA *00A - 31 to give the
processor access to the Filter Compute Engine
Instruction RAMS and Coefficient RAMS.
4. Load the new filter configuration.
5. Load any other channel registers.
6. Clear the mPHold bit in register IWA *00A - 31.
7. Do a software channel reset by writing to IWA *019.
8. Enable the serial outputs (GWA F801) and interrupts
(GWA F802).
9. Generate a SYNCI to enable the input data or to
synchronize the processing to external events or
generate a SYNCO by writing to GWA F809.
NOTE: For the latter method, the SYNCO pin must be connected to
the SYNCI pin.
FN4557.6
August 17, 2007
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