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参数资料
型号： HSP50216KIZ
厂商： Intersil
文件页数： 39/58页
文件大小： 0K
描述： IC DOWNCONVERTER DGTL 4CH 196BGA
标准包装： 1
功能： 降频器
RF 型： W-CDMA
封装/外壳： 196-LFBGA
包装： 托盘
HSP50216
TABLE 24. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 1 (IWA = *015h)
P(31:0)
31:24
23:16
15:8
7:0
FUNCTION
Fourth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 31:24.
Third serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 23:16.
Second serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 for functional description of bits 15:8.
First serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D.
Bit
7
6:3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
2:0
000
001
010
011
100
101
110
111
Function
Sync generated. When set, a sync pulse is generated with the data slot (Serial Data Output 1 only, i.e., the sync is only
associated with Output 1). Set to zero for Output 2, SD2x.
Word width/format. All fixed point data is twos complement. The data is rounded (asymmetrically, with saturation) to the
desired number of bits.
0-bit, fixed point (actually 1-bit position is used).
4-bit, fixed point.
6-bit, fixed point.
8-bit, fixed point.
10-bit, fixed point.
12-bit, fixed point.
16-bit, fixed point.
20-bit, fixed point.
24-bit, fixed point.
32-bit fixed (8 LSBs are zeroed).
32-bit, floating point, IEEE format.
All other codes are invalid.
Note: Floating point format is only available on the Serial Data Output 1. Code 1010 is invalid on Serial Data Output 2.
Data type
Zeros
I1 (data routed from FIFO and AGC path).
Q1 (data routed from FIFO and AGC path).
Magnitude of I1/Q1.
Phase (or d φ /dt) of I1/Q1.
I2 (data routed directly from the filter processor).
Q2 (data routed directly from the filter processor).
AGC gain of I1/Q1 path.
The filter processor must be programmed appropriately to route the data to I1/Q1 or I2/Q2.
NOTE:
Disable a slot by setting the 8-bit word to 00h. When disabled, a slot still uses one clock period. If, for example, the slots are
programmed to 16-bit, disabled, 16-bit, there would a one clock idle period between the two 16-bit data words.
If a new data sample occurs before the current set of data has been output, the new data will preempt the output and the first slot of
the new data will begin immediately. If a late sync was programmed, it will not occur.
0 1 2 3 4 5 6 7 8 9 ABCDEF 0 1 2 3 4 5 6 7 8 9 ABCDEF
I, Q
MAG
PH
AGC
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 ZZZZZZZZ
Z 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 Z Z Z Z Z Z Z Z (MSB zero unless shifted)
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 ZZZZZZZZZZZZZZ
Z 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 Z Z Z Z Z Z Z Z Z Z Z Z Z Z (MSB zeroed)
TABLE 25. SERIAL DATA OUTPUT 1 CONTENT/FORMAT REGISTER 2 (IWA = *016h)
P(31:0)
31:24
23:16
15:8
7:0
FUNCTION
Set to zero.
Seventh serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Sixth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8.
Fifth serial slot in Serial Data Output 1 (SD1x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.
39
FN4557.6
August 17, 2007
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