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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 14/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
Sample filter #2 requires:
? 32 + 32 + 128 + 8 = 200 data RAM locations
? (95+1)/2=48 coefficient RAM location (resampler and HBF
coefficients are in ROM).
Illustrating this concept with Filter Example #3, a higher speed
filter chain might be comprised of one 19 tap decimate-by-2
halfband filter followed by a 30 tap shaping FIR filter with no
decimation. The program for this example could be:
SAMPLE FILTER #3 PROGRAM
The number of clock cycles required to compute an output
for Sample filter #2 is calculated as follows:
SAMPLE FILTER #2 CLOCK CYCLES CALCULATION
CLOCK
STEP
0
1
INSTRUCTION
Wait for enough input samples (2 in this case)
FIR
Type = even symmetry
CYCLES
20
8
14
4
FUNCTION PERFORMED
Halfband 1 compute clocks
(5 per compute x 4 computes)
Halfband 1 input sample writes (8 input samples)
Halfband 2 compute clocks
(7 per compute x 2 computes)
Halfband 2 input sample writes (4 input samples)
19 taps
Halfband
Decimate by 2
Compute one output
Memory block size 32
Memory block start at 0
Coefficient block start at 18
Output to step 2
Reset wait count
48
2
6
1
1
1
105
95 tap symmetric FIR, 2 clocks per tap
FIR input sample writes (2 input samples)
resampler (6 taps, nonsymmetric)
Resampler input sample write (1 input samples)
Jump instruction
Wait instruction
Clock cycles per output
2
3
FIR
Type = even symmetry
30 taps
Decimate by 1
Compute one output
Memory block size 64
Memory block start at 32
Coefficient block start at 64
Step size 1
Output to AGC
Jump, Unconditional, to 0
Total decimation is 8, so the input sample rate for the FIR
chain (CIC output rate) could be up to:
f CLK /(ceil(105/8)) = f CLK /14.
The number of clock cycles required to compute an output
for Sample filter #3 is calculated as follows:
SAMPLE FILTER #3 CLOCK CYCLES CALCULATION
With a 65MHz clock, this would support a maximum input
sample rate to the FIR processor of 4.6MHz and an output
sample rate up to 0.580MHz. The shaping filter impulse
response length would be:
(95 x 2)/580,000 = 82 μ s.
The maximum output sample rate is dependent on the
length and number of FIRs and their decimation factors.
CLOCK
CYCLES
6
2
15
1
1
1
26
FUNCTION PERFORMED
19 tap halfband, one output
halfband input writes (2 input samples)
30 tap symmetric FIR, 2 taps per clock
1 FIR input write
1 wait
1 jump
Clock cycles per output
For Filter Example #3 and a 65MSPS input, the maximum
FIR input rate would be 65MSPS/ceil(26/2) = 5MSPS giving
a decimate-by-2 output sample rate of 2.5MSPS. At
70MSPS, the FIR could have up to 34 taps with the same
output rate.
Channels 0, 1, 2 and 3 can be combined in a polyphase
structure for increased bandwidth or improved filtering.
14
FN4557.6
August 17, 2007
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相关代理商/技术参数 |
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