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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 40/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
TABLE 26. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 1 (IWA = *017h)
P(31:0)
31:24
23:16
15:8
7:0
P(31:0)
31:24
23:16
15:8
7:0
P(15:0)
N/A
P(15:0)
N/A
P(15:0)
N/A
FUNCTION
Fourth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Third serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Second serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8.
First serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.
TABLE 27. SERIAL DATA OUTPUT 2 CONTENT/FORMAT REGISTER 2 (IWA = *018h)
FUNCTION
Set to zero
Seventh serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 23:16.
Sixth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 15:8.
Fifth serial slot in Serial Data Output 2 (SD2x). x = A, B, C or D. See bits 7:0 of Table 24 for functional description of bits 7:0.
TABLE 28. SOFTWARE RESET REGISTER (IWA = *019h)
FUNCTION
Writing to this location resets the following activities of the functional block indicated.
Input Format/Select, NCO, Mixer and CIC.
Clears any pending enable in each channel's input demultiplexer function, loads the CIC decimation counter (the load value
is indeterminate if the decimation counter preload register has not been loaded), clears all processing enables (stops all
processing in the data path, but does not clear the data path registers).
Filter Compute Engine:
Resets the Read/Write pointers, fetch instruction 31 and start the filter program execution.
AGC:
Resets the compute blocks in both the forward and loop filter blocks (any calculations in progress are lost).
Cartesian-to-Polar Coordinate Converter:
Resets the compute blocks (any calculations in progress are lost).
FIFO:
Resets counter (clears the FIFO, all data is lost).
Resampler Timing NCO:
Clears the slave (active) frequency registers and clears the phase accumulator.
Output Section:
Resets the serial output section (clears all registers, counters, and flags but does not clear the configuration registers).
Self Test Control:
Resets the self test control logic of the front end (Input Format/Select, NCO, Mixer, and CIC) and the back end (Filter Compute
Engine, AGC, and Cartesian-to-Polar Coordinate Converter).
TABLE 29. CHANNEL TIMING ADVANCE STROBE REGISTER (IWA = *01Ah)
FUNCTION
Writing to this location inserts one extra data sample in the CIC to FIR path by repeating a sample. Used for shifting the FIR filter
compute engine timing.
TABLE 30. CHANNEL TIMING RETARD STROBE Register (IWA = *01Bh)
FUNCTION
Writing to this location deletes one data sample in the CIC to FIR path. Used for shifting the FIR filter compute engine timing.
40
FN4557.6
August 17, 2007
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相关代理商/技术参数 |
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