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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 29/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
Microprocessor Interface
15:0
M
U
31:16
31:0
INTERNAL READ DATA BUS
X
E
RD
L
FROM OUTPUT FIFO
STATUS
S
P(15:0)
A
T
C
H
en
>
R
E
G
15:0
31:0
INTERNAL
WRITE DATA BUS
WR
en
>
R
E
G
31:16
INTERNAL
ADDRESS BUS
E
>
>
A(2:0)
D
E
C
O
D
E
=0
=1
= 2 or 3
=2
R
en
G
RST
F
F
>
F
F
>
F
F
>
F
F
AND
G
A
T
I
N
G
SYNC’d
WR
CLK
SPECIAL LOW
METASTABILITY
CELL
TO TARGET
REGISTERS
CE
(GATING NOT SHOWN)
Data reads can be direct, indirect or FIFO-like depending on
the data that is being read. The status register is read directly
at direct (external) address 3, ADD(2:0) = 3. Readback of
internal registers and memories is indirect. The 16-bit indirect
(internal) address of the desired read source is first written to
direct (external) address 3, ADD(2:0) = 3, to select the data.
The data can then be read at direct (external) addresses
ADD(2:0) = 0 and 1 (bits 15:0 at address 0 and 31:16 at
address 1). The data types available via the indirect read are
listed in the Tables of Indirect Read Address (IRA) Registers.
(Note that the μ PHold bit contained in the target register at
Indirect Write Address (IWA) = *00Ah must be set to suspend
the filter compute engine before the coefficient RAM and
instruction bit fields can be written to or read from.)
The HSP50216 output data from the four channels is
available through the microprocessor interface as well as from
the serial data outputs. A FIFO-like interface is used to read
the output data through the microprocessor interface. When
new output data is available, it is loaded into a FIFO in a user
programmed order (for details on the programming order, see
Tables of Global Write Address (GWA)
Registers (GWA) = F820h - F83Fh). It can then be read, 16
bits at a time, at direct address 2, ADD(2:0) = 2. At the end of
each read, the FIFO counter is advanced to the next location.
29
INTERNAL
READ SIGNAL
This allows a DMA controller to read all of the data with
successive reads to a single direct address. No writes or other
interaction is required. The FIFO counter is reset and
reloaded by each interrupt signal, see GWA F802h. New data
in the FIFO is also indicated in the status register located at
direct address ADD(2:0) = 3 if a polled mode is preferred. The
eight data types available, for each of the four channels, via
this interface are: I(23:8), I(7:0) + 8 Zeroes, Q(23:8),
Q(7:0) + 8 Zeroes, Mag(23:8), Mag(7:0) + 8 Zeroes, Phase
(15:0), and AGC (15:0). The upper bits of I, i.e., I(23:8), and Q,
i.e., Q(23:8), are not rounded to 16 bits. This interface can
read the data from all the channels that are synchronized.
However, because a common FIFO is used and the FIFO is
reset and reloaded by each interrupt, it cannot be used for
asynchronous channels.
The direct address map for the microprocessor interface is
shown in the TABLE OF MICROPROCESSOR DIRECT
READ/WRITE ADDRESSES and the procedures for reading
and writing to this interface are provided below. The bit field
details for each indirect read and write address are provided
in the Table of Indirect Read Address (IRA) Registers,
Tables of Indirect Write Address (IWA) Registers (Tables 3
through 34) and Tables of Global Write Address (GWA)
Registers (GWA) Registers (Tables 35 through 45).
FN4557.6
August 17, 2007
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