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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 37/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
TABLE 22. AGC/DISCRIMINATOR CONTROL REGISTER (IWA = *013h)
P(15:0)
15:11
10
9
FUNCTION
Set to zero.
μ P AGC loop gain select.
Enable filter compute engine control of AGC loop gain. When this bit is set, bit 28 in the filter compute engine destination field selects
which loop gain to use with that filter output’s gain error. Setting bit 10 overrides this bit and forces a loop gain 1.
10:9
00
10
01
11
FUNCTION
Loop Gain 0 ( μ P controlled)
Loop gain 1 ( μ P controlled)
Loop Gain controlled by filter compute engine
Loop 1 ( μ P override of filter compute engine)
8
Mean/Median. This bit controls the settling mode of the AGC. Mean mode settles to the mean of the signal and settles asymptotically
to the final value. Median mode settles to the median and settles with a fixed step size. This mode settles faster and more predictably,
but will have more AM after settling.
1
0
Mean mode
Median mode
7
6
5
Set this bit to 1 to get a dphi/dt output without having to feedback through the filter compute engine .
Unused. Set to zero.
PhaseOutputSel
1
0
d φ /dt
Phase
4:3
2:0
DiscShift(1:0). Shifts the phase up 0, 1, 2, or 3-bit positions, discarding the bits shifted off the top. This makes the phase modulo 360,
180, 90, or 45 degrees to remove PSK modulation. The resulting phase is 18 bits.
DiscDelay(2:0). Sets the delay, in sample times, for the d φ /dt calculation.
000
111
1
8
TABLE 23. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h)
P(31:0)
31:29
28
Set to zero.
Sync polarity
FUNCTION
1
0
Active low (low for one serial clock per word with a sync).
Active high.
27:26
25:24
Reserved, set to zero.
Sync position. This applies to all time slots in the serial output. The Sync programming is associated with the SD1x serial output data
stream (x = A, B, C, or D).
00
01
1X
Sync is asserted during the serial clock period prior to the first data bit of the serial word (early sync).
Sync is asserted during the clock period following the last data bit of the word (late sync).
Sync is asserted during the serial clock period of the first data bit of the serial word (coincident sync).
23:22
Reserved, set to zero.
37
FN4557.6
August 17, 2007
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相关代理商/技术参数 |
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| HSP50306 WAF | 制造商:Intersil Corporation 功能描述: |
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