参数资料
型号: HSP50216KIZ
厂商: Intersil
文件页数: 48/58页
文件大小: 0K
描述: IC DOWNCONVERTER DGTL 4CH 196BGA
标准包装: 1
功能: 降频器
RF 型: W-CDMA
封装/外壳: 196-LFBGA
包装: 托盘
HSP50216
Electrical Specifications
V CC = 3.3V ± 0.15V, T A = -40°C to +85°C Industrial (Continued)
PARAMETER
SYMBOL
MIN
MAX
UNITS
MICROPROCESSOR WRITE TIMING
P(15:0) Setup Time to Rising Edge of WR
P(15:0) Hold Time from Rising Edge of WR
A(1:0) Setup Time to Rising Edge of WR
A(1:0) Hold Time from Rising Edge of WR
CE Setup Time to Rising Edge of WR
CE Hold Time from Rising Edge of WR
WR Low Time
t DSW
t DHW
t ASW
t AHW
t CSW
t CHW
t WL
10
-2
10
-2
10
-2
5
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
MICROPROCESSOR READ TIMING
A(1:0) Setup Time to FALLING Edge of RD
A(1:0) Hold Time from RISING Edge of RD
RD Enable Time
RD Disable Time (Note 9)
RD to P(15:0) Data Valid Time
CE Setup Time to Falling Edge of RD
CE Hold Time from Rising Edge of RD
t ASR
t AHR
t RE
t RD
t DV
t CSR
t CHR
8
-2
-
-
-
8
-2
-
-
11.5
8
12
-
-
ns
ns
ns
ns
ns
ns
ns
SERIAL CLOCK OUTPUT TIMING
CLK to Serial Data, Sync and SCLK (Divide-by 2 through 16 Modes)
CLK Low to SCLK Low (Divide-by 1 Mode, Note 9)
CLK High to SCLK High (Divide-by 1 Mode, Note 9)
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 2 through 16 Modes,
t PD
t PDL
t PDH
t SKEW1
-
-
-
-1
6.5
6.5
3
1
ns
ns
ns
ns
Note 9)
Time Skew Between SCLK and Serial Data or Serial Sync (Divide-by 1 Mode, Note 9)
t SKEW2
0.5
2
ns
NOTES:
8. The HSP50216 goes into reset immediately on RESET going low and comes out of reset on the 4th rising edge of CLK after RESET goes high.
9. Limits established by characterization and are not production tested.
AC Test Load Circuit
DUT
S 1
C L (NOTE)
±
NOTE - TEST HEAD CAPACITANCE, 40pF (TYP)
I OH
1.5V
I OL
SWITCH S1 OPEN FOR I CCSB AND I CCOP
EQUIVALENT CIRCUIT
48
FN4557.6
August 17, 2007
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