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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 27/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
Serial Data Output Formatter Section
OUTPUT SECTION
I1
Q1
MAG
R
ZERO
M
U
FIXED
TO
FLOAT
ROUND
M
U
X
PARALLEL
TO
SERIAL
&
& O
& R
&
SD1x
PHASE
E
X
&
I2
Q2
GAIN
G
SEQUENCER
1
SYNC
GEN
& O
& R
&
SYNCx
STROBE
ZERO
DELAY
&
& O
PARALLEL
& R
SD2x
M
U
ROUND
TO
SERIAL
&
X
SEQUENCER
2
M
U
X
16
TO μ P
INTERFACE
NOTE: Each serial output has 7 time slots. Each slot can contain I1, Q1, I2, Q2, Mag, phase or d φ /dt. AGC gain, or zeros. Each slot can be 4, 6, 8,
10, 12, 16, 20, 24, or 32 (24 + 8 zeros) bits or disabled. Output 1 can also be 32-bit floating point. Slots can be disabled. A disabled slot will be one
clock wide if there are other active slots following. A sync can be asserted with any or all slots following. A sync can be asserted with any or all slots
in output 1. The serial output can be delayed from 0 to 4095 serial clock periods from the input strobe. The serial outputs are always MSB first. The
sync position applies to all time slots and can be one clock prior to the first data bit, aligned with the first data bit, or one clock after the last data bit.
Serial Data Output Control Register
The serial data output control register contains sync position
and polarity (SYNCA, B, C or D), channel multiplexing, and
scaling controls for the SD1x and SD2x (x = A, B, C or D)
serial outputs (see Microprocessor Interface section,
Table 23, “SERIAL DATA OUTPUT CONTROL REGISTER
(IWA = *014h),” on page 37).
Channel Routing Mask
The multiplexing mask bits for each channel (see
Microprocessor Interface section, Table 23, IWA *014h bits
19:16 for SD1x or bits 15:12 for SD2x) can be used to
enable that channel’s output to any of the four serial outputs.
These bits control the AND gates that mask off the channels,
so a zero disables the channel’s connection to that output.
27
To configure more than one channel's output onto a serial
data output, the SD1 serial outputs and syncs from each
channel (0, 1, 2 and 3) are brought to each of the SD1 serial
output sections and the SD2 serial outputs are brought to
each of the SD2 serial output sections (the syncs are only
associated with the SD1 serial outputs). There, the four
outputs are AND-ed with the multiplexing mask programmed
in the serial data output control registers of channels
0 through 3 and OR-ed together. By gating off the channels
that are not wanted and delaying the data from each desired
channel appropriately, the channels can be multiplexed into
a common serial output stream. It should be noted that in
order to multiplex multiple channels onto a single serial data
stream the channels to be multiplexed must be synchronous.
FN4557.6
August 17, 2007
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