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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 18/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
28:18
FUNCTION
Destination
Destination Field Bit Mapping
DESCRIPTION
28 27 26
25
24
23
22
21
20
19
18
AGCLFGN AGCLF
Path1
Path0
OS
FB
F4
F3
F2
F1
F0
AGCLFGNAGC loop gain select. Only applies to Path 1.
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGCLF
AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Path(1:0) Back End Data Routing Path Selection.
00Route output back to filter compute engine input to another FIR in the filter chain.
01Route output through the FIFO and AGC forward path to the cartesian-to-polar coordinate
converter conversion and output (I1, Q1, magnitude, phase, gain) and also to route to a dis-
criminator (i.e., d φ /dt FIR).
10Route output directly to the output, bypassing the FIFO and AGC (I2, Q2). This path also
routes to next channel FIR input.
OS
FB
F(4:0)
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input (magnitude goes to the
I input and dphi/dt goes to the Q input). Provided for discriminator filtering.
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the car-
tesian to polar coordinate converter output, these bits tell which filter sequencer step gets it
as an input.
31:29
Round Select
31:29
000
001
010
011
100
101
110
111
Round Select (Add rounding bit at specified location).
2 -24 , use this code when downshifting is not used.
2 -23
2 -22
2 -21
2 -20
2 -19
2 -18
no rounding.
Provided for use with the coefficient down-shift bits.
41:32
Data Memory
Block Start
Memory block base address, 0-1023, 0-383 are valid for the HSP50216.
44:42
Data Memory
Block Size
44:42
0
1
2
3
4
5
6
7
Block Size.
8
16
32
64
128
256
512
1024
(modulo addressing is used).
52:45
Data Memory
Block-to-Block Step
18
0-255, usually equal to the decimation factor for the FIR in this instruction.
FN4557.6
August 17, 2007
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