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| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 5/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
Pin Descriptions
(Continued)
NAME
OUTPUTS
SD1A
SD2A
SD1B
SD2B
SD1C
SD2C
SD1D
SD2D
SCLK
SYNCA
SYNCB
SYNCC
SYNCD
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2,
magnitude, phase, frequency (d φ /dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0,
1, 2 and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in
a programmable order. See Serial Data Output Formatter Section.
Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data
to a second destination or to output two words at a time for higher sample rates. SD2A has the same
programmability as SD1A except that floating point format is not available. See Serial Data Output
Formatter Section and Microprocessor Interface section .
Serial Data Output 1B. See description for SD1A.
Serial Data Output 2B. See description for SD2A.
Serial Data Output 1C. See description for SD1A.
Serial Data Output 2C. See description for SD2A.
Serial Data Output 1D. See description for SD1A.
Serial Data Output 2D. See description for SD2A.
Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The
polarity of SCLK is programmable.
Serial Data Output 1A sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCA is programmable.
Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCB is programmable.
Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCC is programmable.
Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of
data. The polarity and position of SYNCD is programmable.
MICROPROCESSOR INTERFACE
P(15:0)
ADD(2:0)
WR
or
DSTRB
RD
or
RD/WR
μ P MODE
CE
INTRPT
I/O
I
I
I
I
I
O
5
Microprocessor Interface Data bus. See “Microprocessor Interface” on page 29 . P15 is the MSB.
Microprocessor Interface Address bus. ADD2 is the MSB. See “Microprocessor Interface” on page 29 .
Note: ADD2 is not used but designated for future expansion.
Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control,
μ P MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the
internal write holding register to the target register specified) occur on the low to high transition of WR when
CE is asserted (low). When the μ P MODE control is high this input functions as a data read/write strobe.
In this mode with RD/WR low data transfers (from either P(15:0) to the internal write holding register or
from the internal write holding register to the target register specified) occur on the low to high transition of
Data Strobe. With RD/WR high the data from the address specified is placed on P(15:0) when Data Strobe
is low. See “Microprocessor Interface” on page 29 .
Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control,
μ P MODE, is a low the data from the address specified is placed on P(15:0) when RD is asserted (low)
and CE is asserted (low). When the μ P MODE control is high this input functions as a Read/Write control
input. Data is read from P(15:0) when high or written to the appropriate register when low. See
“Microprocessor Interface” on page 29 .
Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the
Microprocessor Interface. Internally pulled down. See “Microprocessor Interface” on page 29 .
Microprocessor Interface Chip Select. Active low. This pin has the same timing as the address pins.
Microprocessor Interrupt Signal. Asserted for a programmable number of clock cycles when new data is
available on the selected Channel.
FN4557.6
August 17, 2007
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