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参数资料
| 型号： | HSP50216KIZ |
| 厂商： | Intersil |
| 文件页数： | 25/58页 |
| 文件大小： | 0K |
| 描述： | IC DOWNCONVERTER DGTL 4CH 196BGA |
| 标准包装： | 1 |
| 功能： | 降频器 |
| RF 型： | W-CDMA |
| 封装/外壳： | 196-LFBGA |
| 包装： | 托盘 |
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HSP50216
The median mode minimizes the settling time. This mode
TABLE 1. MAG/PHASE BIT WEIGHTING
uses a fixed gain adjustment with only the direction of the
adjustment controlled by the gain error. This makes the
settling time independent of the signal level.
BIT
23 (MSB)
MAGNITUDE
2 2
180
PHASE ( o )
For example, if the loop is set to adjust 0.5dB per output
sample, the loop gain can slew up or down by 16dB in 16
symbol times, assuming a 2 samples per symbol output
sample rate. This is called a median settling mode because
the loop settles to where there is an equal number of
magnitude samples above and below the threshold. The
disadvantage of this mode is that the loop will have a wander
(dither) equal to the programmed step size. For this reason,
it is advisable to set one loop gain for fast settling at the
beginning of the burst and the second loop gain for small
adjustments during tracking.
In the median mode, the maximum gain step is
approximately 3dB/output. The step is fixed (it does not
decrease as the error decreases) so a large gain will cause
AM on the output at least that large. The gain should be
lowered after the settling. The fixed gain step is set by the
programmable AGC loop gain register IWA *010h.
For median mode, The AGC gain limits register sets the
minimum and maximum limits on the AGC gain. The total
AGC gain range is 96dB, but only a portion of the range
should be needed for most applications. For example, with a
16-bit output to a processor, the 16 bits may be sufficient for
all but 24dB of the total input range possible. The AGC
would only need to have a range of 24dB. This allows faster
settling and the AGC would be at its maximum gain limit
except when a high power signal was received. The AGC
may be disabled by setting both limits to the same value.
The median settling mode is enabled by setting IWA register
*013h bit 8 to 0 while the mean loop settling mode is
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
+ π /2
400000 3ff fff
Q
2 1
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
2 -8
2 -9
2 -10
2 -11
2 -12
2 -13
2 -14
2 -15
2 -16
2 -17
2 -18
2 -19
2 -20
2 -21
90
45
22.5
11.25
5.625
2.8125
1.40625
0.703125
0.3515625
0.17578125
0.087890625
0.043945312
0.021972656
0.010986328
0.005483164
0.002741582
0.001370791
0.0006853955
0.00034269775
0.00017134887
0.00008567444
0.00004283722
0.00002141861
π /2
400000 3fffff
Q
selected by setting bit 8 to 1.
Cartesian to Polar Converter
7fffff
± π
800000
I 000000
0
ffffff
7fffff
π
800000
I
000000
0
ffffff
The Cartesian to Polar converter computes the magnitude
and phase of the I/Q vector. The I and Q inputs are 24 bits.
bfffff c00000
- π /2
bfffff c00000
3 π /2
The converter phase output is 24 bits, MSB’s routed to the
output formatter and all 24 bits routed to the frequency
discriminator. The 24-bit output phase can be interpreted
either as two’s complement (-0.5 to approximately 0.5) or
unsigned (0.0 to approximately 1.0), as shown in Figure 2.
The phase conversion gain is 1/2 π . The phase resolution is
24 bits. The 24-bit magnitude is unsigned binary format with
a range from 0 to 2.32. The magnitude conversion gain is
1.64676. The magnitude resolution is 24 bits. The MSB is
always zero.
Table 1 details the phase and magnitude weighting for the 16
bits output from the PDC.
25
FIGURE 2. PHASE BIT MAPPING OF COORDINATE
CONVERTER OUTPUT
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the output formatter or frequency discriminator.
If a new input sample arrives before the end of the 17 cycles,
the results of the computations up until that time, are
latched. This latching means that an increase in speed
causes only a decrease in resolution. Table 2 details the
exact resolution that can be obtained with a fixed number of
clock cycles up to the required 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
FN4557.6
August 17, 2007
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