参数资料
| 型号： | IP-FIR |
| 厂商： | Altera |
| 文件页数： | 15/76页 |
| 文件大小： | 0K |
| 描述： | IP FIR COMPILER |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 有限脉冲响应编译器 |
| 许可证： | 初始许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
2. Getting Started
Design Flows
The FIR Compiler MegaCore ? function supports the following design flows:
■
■
DSP Builder : Use this flow if you want to create a DSP Builder model that
includes a FIR Compiler MegaCore function variation.
MegaWizard? Plug-In Manager : Use this flow if you would like to create a FIR
Compiler MegaCore function variation that you can instantiate manually in your
design.
This chapter describes how you can use a FIR Compiler MegaCore function in either
of these flows. The parameterization is the same in each flow and is described in
After parameterizing and simulating a design in either of these flows, you can
compile the completed design in the Quartus II software.
DSP Builder Flow
Altera’s DSP Builder product shortens digital signal processing (DSP) design cycles
by helping you create the hardware representation of a DSP design in an algorithm-
friendly development environment.
DSP Builder integrates the algorithm development, simulation, and verification
capabilities of The MathWorks MATLAB ? and Simulink ? system-level design tools
with Altera Quartus ? II software and third-party synthesis and simulation tools. You
can combine existing Simulink blocks with Altera DSP Builder blocks and MegaCore
function variation blocks to verify system level specifications and perform simulation.
In DSP Builder, a Simulink symbol for the FIR Compiler appears in the MegaCore
Functions library of the Altera DSP Builder Blockset in the Simulink library browser.
You can use the FIR Compiler in the MATLAB/Simulink environment by performing
the following steps:
1. Create a new Simulink model.
2. Select the FIR Compiler block from the MegaCore Functions library in the
Simulink Library Browser, add it to your model, and give the block a unique
name.
3. Double-click the FIR Compiler block in your model to display IP Toolbench and
click Step 1: Parameterize to parameterize a FIR Compiler MegaCore function
variation. For an example of how to set parameters for the FIR Compiler block,
4. Click Step 2: Generate in IP Toolbench to generate your FIR Compiler MegaCore
5. Connect your FIR Compiler MegaCore function variation block to the other
blocks in your model.
? May 2011
Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| IP-NCO | IP NCO COMPILER |
| IP-NIOS | IP NIOS II MEGACORE |
| IP-PCI/MT64 | IP PCI 64BIT MASTER/TARGET |
| IP-PCIE/8 | IP PCI EXPRESS, X8 |
| IP-POSPHY4 | IP POS-PHY L4 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IP-FIRII | 功能描述:开发软件 FIR Compiler II MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPFLBPT2 | 制造商:Carlo Gavazzi 功能描述:IL 35MM MUSH P-P PL 22MM RED |
| IPG1-0-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-41-203-90 | 制造商:Sensata Technologies 功能描述:1 Pole |
| IPG1-1-51-103-A-00-V | 制造商:Sensata Technologies 功能描述:Circuit Breaker Magnetic 1Pole 10A 65VDC |
发布紧急采购，3分钟左右您将得到回复。